--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/mcsi-rx/sync_inputs.v	Fri Oct 11 21:11:24 2024 +0000
@@ -0,0 +1,35 @@
+/*
+ * This Verilog module captures the input synchronizer logic: passing
+ * all 3 MCSI inputs through double-DFF synchronizers to bring them into
+ * our internal clock domain.
+ */
+
+module sync_inputs (IntClk, MCSI_CLK_raw, MCSI_CLK_sync, MCSI_FS_raw,
+		    MCSI_FS_sync, MCSI_Din_raw, MCSI_Din_sync);
+
+input IntClk;
+input MCSI_CLK_raw, MCSI_FS_raw, MCSI_Din_raw;
+output MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
+reg MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
+
+reg MCSI_CLK_sync1, MCSI_FS_sync1, MCSI_Din_sync1;
+
+always @(posedge IntClk)
+	MCSI_CLK_sync1 <= MCSI_CLK_raw;
+
+always @(posedge IntClk)
+	MCSI_CLK_sync <= MCSI_CLK_sync1;
+
+always @(posedge IntClk)
+	MCSI_FS_sync1 <= MCSI_FS_raw;
+
+always @(posedge IntClk)
+	MCSI_FS_sync <= MCSI_FS_sync1;
+
+always @(posedge IntClk)
+	MCSI_Din_sync1 <= MCSI_Din_raw;
+
+always @(posedge IntClk)
+	MCSI_Din_sync <= MCSI_Din_sync1;
+
+endmodule