FreeCalypso > hg > fc-pcm-if
view fpga/mcsi-rx/sync_inputs.v @ 9:62579cfff4fc
fc-mcsi-rxtx: more proper integration with ttyhacks
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 28 Oct 2024 06:02:04 +0000 |
parents | b3190839cce3 |
children |
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/* * This Verilog module captures the input synchronizer logic: passing * all 3 MCSI inputs through double-DFF synchronizers to bring them into * our internal clock domain. */ module sync_inputs (IntClk, MCSI_CLK_raw, MCSI_CLK_sync, MCSI_FS_raw, MCSI_FS_sync, MCSI_Din_raw, MCSI_Din_sync); input IntClk; input MCSI_CLK_raw, MCSI_FS_raw, MCSI_Din_raw; output MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync; reg MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync; reg MCSI_CLK_sync1, MCSI_FS_sync1, MCSI_Din_sync1; always @(posedge IntClk) MCSI_CLK_sync1 <= MCSI_CLK_raw; always @(posedge IntClk) MCSI_CLK_sync <= MCSI_CLK_sync1; always @(posedge IntClk) MCSI_FS_sync1 <= MCSI_FS_raw; always @(posedge IntClk) MCSI_FS_sync <= MCSI_FS_sync1; always @(posedge IntClk) MCSI_Din_sync1 <= MCSI_Din_raw; always @(posedge IntClk) MCSI_Din_sync <= MCSI_Din_sync1; endmodule