/*
 * This Verilog module captures the UART output logic.
 */

module uart_tx (IntClk, Tx_trigger, Tx_data, UART_out);

input IntClk;
input Tx_trigger;
input [15:0] Tx_data;
output UART_out;
reg UART_out;

reg tx_active;
reg [5:0] clk_div;
reg [4:0] bit_count;
reg [17:0] shift_reg;

initial begin
	tx_active = 1'b0;
	UART_out = 1'b1;
end

always @(posedge IntClk)
	if (!tx_active && Tx_trigger)
	    begin
		tx_active <= 1'b1;
		UART_out <= 1'b0;
		clk_div <= 6'd0;
		shift_reg <= {Tx_data[15:8],2'b01,Tx_data[7:0]};
		bit_count <= 5'd0;
	    end
	else if (tx_active)
	    begin
		clk_div <= clk_div + 6'd1;
		if (clk_div == 6'd63)
		    begin
			UART_out <= shift_reg[0];
			shift_reg <= {1,shift_reg[17:1]};
			bit_count <= bit_count + 5'd1;
			if (bit_count == 5'd19)
				tx_active <= 1'b0;
		end
	end

endmodule