/*
 * The logic implemented in this module detects if MCSI_CLK is running or not,
 * for the purpose of visual indication on a LED.  In the future Tx-capable
 * FPGA, this logic will also be used to reset the Tx buffer when the clock
 * stops.
 */

module clk_check (IntClk, MCSI_CLK_sync, MCSI_CLK_running);

input IntClk;
input MCSI_CLK_sync;
output MCSI_CLK_running;

reg [15:0] shift_reg;

always @(posedge IntClk)
	shift_reg <= {shift_reg[14:0],MCSI_CLK_sync};

assign MCSI_CLK_running = (shift_reg != 16'h0000) && (shift_reg != 16'hFFFF);

endmodule