/*
 * This Verilog module captures the logic that receives 16-bit PCM samples
 * from MCSI.  This logic block also detects loss of frame sync.
 */

module mcsi_rx (IntClk, MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge,
		PCM_sample_out, PCM_sample_strobe, FS_lost);

input IntClk;
input MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge;
output [15:0] PCM_sample_out;
output PCM_sample_strobe;
output FS_lost;

reg [15:0] shift_reg;
reg [6:0] bit_count;

always @(posedge IntClk)
	if (MCSI_CLK_negedge)
	    begin
		shift_reg <= {shift_reg[14:0],MCSI_Din_sync};
		if (MCSI_FS_sync)
			bit_count <= 7'd0;
		else if (bit_count != 7'd127)
			bit_count <= bit_count + 7'd1;
	end

assign PCM_sample_out = shift_reg;
assign PCM_sample_strobe = MCSI_CLK_negedge && (bit_count == 7'd16);
assign FS_lost = (bit_count == 7'd127);

endmodule