view fpga/tools/yosys-wrap @ 8:ee14dd81bba1

sw/Makefile: add mcsi-rxtx
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 28 Oct 2024 01:45:32 +0000
parents 4624f3da093a
children
line wrap: on
line source

#!/bin/sh

if [ $# -lt 3 ]
then
	echo "usage: $0 top-module json-output verilog-src..." 1>&2
	exit 1
fi

top="$1"
json="$2"

shift
shift

rm -f "$json"
yosys -p "synth_ice40 -top $top -json $json" "$@"

if [ -f "$json" ]
then
	echo "$json created, declaring success"
	exit 0
else
	echo "$json NOT created, declaring error"
	exit 1
fi