fc-selenite: src/cs/drivers/drv_core/abb/abb.c annotate

annotate src/cs/drivers/drv_core/abb/abb.c @ 147:0d96c28dedb1

src/cs/layer1/include/l1_const.h: BIG_SMALL_SLEEP added

author	Mychaela Falconia <falcon@freecalypso.org>
date	Wed, 06 Feb 2019 23:00:51 +0000
parents	b6a5e36de839
children	4f40ae165be4

rev	line source
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /**********************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 /* product is protected under copyright law and trade secret law as an */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 /* rights reserved. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 /* Filename : abb.c */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 /* Description : Functions to drive the ABB device. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 /* The Serial Port Interface is used to connect the TI */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 /* Analog BaseBand (ABB). */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 /* It is assumed that the ABB is connected as the SPI */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 /* device 0. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 /* Author : Pascal PUEL */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 /* Version number : 1.3 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 /* Date and time : 08/22/03 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 /* Previous delta : Creation */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 /**********************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #include "l1sw.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #include "chipset.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #include "board.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 #include "rf.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #include "swconfig.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #include "sys.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #include "abb.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #include "l1_macro.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #include "l1_confg.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 #include "clkm/clkm.h" // for wait_ARM_cycles function
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 #include "abb_inline.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 #include "ulpd/ulpd.h" // for FRAME_STOP definition
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #include "nucleus.h" // for NUCLEUS functions and types
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #include "l1_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #include "main/sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #include "rv/general.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #include "sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #if (VCXO_ALGO == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #include "l1_ctl.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 #if (RF_FAM == 35)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #include "l1_rf35.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #if (RF_FAM == 12)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #include "tpudrv12.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #include "l1_rf12.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #if (RF_FAM == 10)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #include "l1_rf10.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #if (RF_FAM == 8)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #include "l1_rf8.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #if (RF_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #include "l1_rf2.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 * The following conditional compilation control is a FreeCalypso addition.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 * TI's original code always configured the BCICONF register with
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 * MESBB and BBCHGEN bits set, enabling both charging and the measurement
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 * resistive divider for the backup battery. However, on our primary
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 * hw targets (Openmoko GTA02 and our own FCDEV3B) Iota's VBACKUP pin
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 * is unconnected, whereas on Mot C139 and Pirelli DP-L10 "alien" hw
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 * the VBACKUP situation is unclear. But at least on our known hw
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 * with VBACKUP unconnected, it is better to leave backup battery charging
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 * and measurement OFF - TI's original config seems to be a drain on
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 * the main battery. Therefore, we are going to leave MESBB and BBCHGEN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 * off until and unless we have a hw target where backup battery charging
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90 * and measurement are appropriate.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define ENABLE_BACKUP_BATTERY 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 #if (ABB_SEMAPHORE_PROTECTION)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 static NU_SEMAPHORE abb_sem;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 /* ABB_Sem_Create() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 /* This function creates the Nucleus semaphore to protect ABB accesses */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103 /* against preemption. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 /* No check on the result. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107 void ABB_Sem_Create(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 // create a semaphore with an initial count of 1 and with FIFO type suspension.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 /* ABB_Wait_IBIC_Access() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 /* This function waits for the first IBIC access. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121 void ABB_Wait_IBIC_Access(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #if (ANLG_FAM ==1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 // (i.e wait 60us + 10% security marge = 66us)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 wait_ARM_cycles(convert_nanosec_to_cycles(66000));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #elif ((ANLG_FAM ==2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 // Wait 6 x 32 KHz clock cycles for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 // (i.e wait 187us + 10% security marge = 210us)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130 wait_ARM_cycles(convert_nanosec_to_cycles(210000));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 /* ABB_Write_Register_on_page() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 /* This function manages all the spi serial transfer to write to an */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 /* ABB register on a specified page. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 SPI_Ready_for_WR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 // set the ABB page for register access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 ABB_SetPage(page);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 // Write value in reg_id
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 ABB_WriteRegister(reg_id, value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 // set the ABB page for register access at page 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 /* ABB_Read_Register_on_page() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 /* This function manages all the spi serial transfer to read one */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 /* ABB register on a specified page. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 /* Returns the real data value of the register. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 SPI_Ready_for_RDWR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 /* set the ABB page for register access */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 ABB_SetPage(page);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 /* Read selected ABB register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 reg_val = ABB_ReadRegister(reg_id);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 /* set the ABB page for register access at page 0 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 return (reg_val); // Return result
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 /* ABB_free_13M() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 /* This function sets the 13M clock working in ABB. A wait loop */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 /* is required to allow first slow access to ABB clock register. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 /* WARNING !! : this function must not be protected by semaphore !! */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 void ABB_free_13M(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 SPI_Ready_for_WR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 // This transmission frees the CLK13 in ABB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 ABB_WriteRegister(TOGBR2, 0x08);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 // Wait for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 ABB_Wait_IBIC_Access();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 // SW Workaround : This transmission has to be done twice.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 ABB_WriteRegister(TOGBR2, 0x08);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 // Wait for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 ABB_Wait_IBIC_Access();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 /* ABB_stop_13M() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 /* This function stops the 13M clock in ABB. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 void ABB_stop_13M(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 SPI_Ready_for_WR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 // Set ACTIVMCLK = 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 ABB_WriteRegister(TOGBR2, 0x04);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 // Wait for first IBIC access
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 ABB_Wait_IBIC_Access();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 /* ABB_Read_Status() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 /* This function reads and returns the value of VRPCSTS ABB register. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 SYS_UWORD16 ABB_Read_Status(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 SPI_Ready_for_WR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 #if ((ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 #if (ANLG_FAM == 1) \|\| (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 reg_val = ABB_ReadRegister(VRPCSTS);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 reg_val = ABB_ReadRegister(VRPCCFG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 #if ((ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 return (reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 /* ABB_on() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 /* This function configures ABB registers to work in ON condition */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 #if ((ANLG_FAM ==2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 SYS_UWORD32 reg;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 if (bRecoveryFlag)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 // RESTITUTE 13MHZ CLOCK TO ABB
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 ABB_free_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 ABB_free_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 SPI_Ready_for_RDWR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 #if (ABB_SEMAPHORE_PROTECTION == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 // This transmission disables MADC,AFC,VDL,VUL modules.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 ABB_WriteRegister(TOGBR1, 0x0155);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 // This transmission disables Band gap fast mode Enable BB charge.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 ABB_WriteRegister(VRPCCTL2, 0x1fc);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 /* ********* DC/DC enabling selection ************************************************************ */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 // This transmission changes the register page in OMEGA for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 SYS_UWORD8 vrpcctrl3_data;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #if (CHIPSET == 9) \|\| (CHIPSET == 10) \|\| (CHIPSET == 11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419 vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 if(modules & DCDC) // check if the DCDC is enabled
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 vrpcctrl3_data \|= 0x0002; // set DCDCEN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 // This access disables the DCDC.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 /* ********************** SELECTION OF TEST MODE FOR ABB ************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 /* ***************************************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 // This transmission enables Omega test register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 ABB_WriteRegister(TAPCTRL, 0x01);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 // This transmission select Omega test instruction.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 ABB_WriteRegister(TAPREG, TSPTEST1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 // This transmission disables Omega test register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 ABB_WriteRegister(TAPCTRL, 0x00);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 /* *************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 // This transmission changes SIM power supply to 3 volts.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 ABB_WriteRegister(VRPCCTRL1, 0x45);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 // This transmission enables selected OMEGA modules.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 if(modules & MADC) // check if the ADC is enabled
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 // This transmission connects the resistive divider to MB and BB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 ABB_WriteRegister(BCICTL1, 0x0005);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 #elif ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 // Restore the ABB checks and debouncing if start on TESTRESETZ
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 // This transmission changes the register page in the ABB for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 // This transmission sets the AFCCK to CKIN/2.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 ABB_WriteRegister(AFCCTLADD, 0x01);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 // This transmission enables the tapreg.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 ABB_WriteRegister(TAPCTRL, 0x01);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 // This transmission enables access to page 2.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 ABB_WriteRegister(TAPREG, 0x01b);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 // This transmission changes the register page in the ABB for usp to pg2.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 ABB_SetPage(PAGE2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 #if (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 // Restore push button environment
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 ABB_WriteRegister(0x3C, 0x07);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 // Restore push button environment
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 ABB_WriteRegister(0x3C, 0xBF);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 /* ********************** SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *****************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 // This transmission enables access to page 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 // reset bit MSKINT1 , if set by TESTRESET
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 reg=ABB_ReadRegister(VRPCSTS) & 0xffe;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 ABB_WriteRegister(VRPCSTS, reg);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 ABB_SetPage(PAGE2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 // Restore default for BG behavior in sleep mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 ABB_WriteRegister(VRPCAUX, 0xBF);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 // Restore default for deboucing length
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 ABB_WriteRegister(VRPCLDO, 0x00F);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 // Restore default for INT1 generation, wait time in switch on, checks in switch on
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 ABB_WriteRegister(VRPCABBTST, 0x0002);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 // This transmission changes the register page in the ABB for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 // This transmission sets tapinst to id code.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 ABB_WriteRegister(TAPREG, 0x0001);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 // This transmission disables TAPREG access.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 ABB_WriteRegister(TAPCTRL, 0x00);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 // This transmission enables BB charge and BB bridge connection for BB measurements.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 #if ENABLE_BACKUP_BATTERY
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 ABB_WriteRegister(BCICONF, 0x060);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 ABB_WriteRegister(BCICONF, 0x000);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 /* ********************** SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *****************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 #if (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 /* ********************** SELECTION OF TEST MODE FOR ABB ****************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 /* ****************************************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 // This transmission enables the tapreg.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 ABB_WriteRegister(TAPCTRL, 0x01);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 // This transmission select ABB test instruction.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 ABB_WriteRegister(TAPREG, TSPEN);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 // This transmission changes the register page in ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 // This transmission enables selected ABB modules.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 ABB_WriteRegister(TOGBR1, modules >> 6);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 // enable MB & BB resistive bridges for measurements
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 if(modules & MADC) // check if the ADC is enabled
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 // This transmission connects the resistive divider to MB and BB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 ABB_WriteRegister(BCICTL1, 0x0001);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 /******* Sleep definition part ****************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 // This transmission changes the register page in the ABB for usp to pg1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 #if (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 ABB_WriteRegister(VRPCCFG, (SLPDLY \| reg));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE \| reg));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579 // This transmission changes the register page in the ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 // SW workaround for initialization of the audio parts of the ABB to avoid white noise
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584 // C.f. BUG1941
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 // Set VDLR and VULR bits
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586 // Write TOGBR1 register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 // This transmission enables selected ABB modules.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 ABB_WriteRegister(TOGBR1, 0x0A);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590 // wait for 1 ms
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 wait_ARM_cycles(convert_nanosec_to_cycles(1000000));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 // Reset VDLS and VULS bits
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594 // Write TOGBR1 register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595 // This transmission enables selected ABB modules.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596 ABB_WriteRegister(TOGBR1, 0x05);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 #if (ABB_SEMAPHORE_PROTECTION == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615 /* ABB_Read_ADC() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617 /* This function manages all the spi serial transfer to read all the */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 /* ABB ADC conversion channels. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619 /* Stores the result in Buff parameter. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622 void ABB_Read_ADC(SYS_UWORD16 *Buff)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	623 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	624 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	625
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	626 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	627 SPI_Ready_for_RDWR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	628 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	629
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	630 #if (ABB_SEMAPHORE_PROTECTION == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	631
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	632 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	633 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	634 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	635 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	636 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	637 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	638 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	639 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	640
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	641 // This transmission changes the register page in the ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	642 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	643
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	644 /* Read all ABB ADC registers */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	645 *Buff++ = ABB_ReadRegister(VBATREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	646 *Buff++ = ABB_ReadRegister(VCHGREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	647 *Buff++ = ABB_ReadRegister(ICHGREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	648 *Buff++ = ABB_ReadRegister(VBKPREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	649 *Buff++ = ABB_ReadRegister(ADIN1REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	650 *Buff++ = ABB_ReadRegister(ADIN2REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	651 *Buff++ = ABB_ReadRegister(ADIN3REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	652
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	653 #if (ANLG_FAM ==1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	654 *Buff++ = ABB_ReadRegister(ADIN4XREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	655 *Buff++ = ABB_ReadRegister(ADIN5YREG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	656 #elif (ANLG_FAM ==2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	657 *Buff++ = ABB_ReadRegister(ADIN4REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	658 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	659 *Buff++ = ABB_ReadRegister(ADIN4REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	660 *Buff++ = ABB_ReadRegister(ADIN5REG);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	661 #endif // ANLG_FAM
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	662
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	663 #if (ABB_SEMAPHORE_PROTECTION == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	664 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	665 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	666 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	667 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	668 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	669 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	670
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	671 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	672 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	673 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	674 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	675 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	676
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	677
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	678
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	679 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	680 /* ABB_Conf_ADC() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	681 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	682 /* This function manages all the spi serial transfer to: */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	683 /* - select the ABB ADC channels to be converted */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	684 /* - enable/disable EOC interrupt */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	685 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	686 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	687 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	688 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	689 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	690 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	691
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	692 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	693 SPI_Ready_for_RDWR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	694 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	695
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	696 #if (ABB_SEMAPHORE_PROTECTION == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	697
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	698 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	699 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	700 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	701 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	702 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	703 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	704 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	705 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	706
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	707 // This transmission changes the register page in the ABB for usp to pg0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	708 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	709
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	710 /* select ADC channels to be converted */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	711 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	712 ABB_WriteRegister(MADCCTRL1, Channels);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	713 #elif ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	714 ABB_WriteRegister(MADCCTRL, Channels);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	715 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	716
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	717 reg_val = ABB_ReadRegister(ITMASK);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	718
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	719 // This transmission configure the End Of Conversion IT without modifying other bits in the same register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	720 if(ItVal == EOC_INTENA)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	721 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	722 else if(ItVal == EOC_INTMASK)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	723 ABB_WriteRegister(ITMASK, reg_val \| EOC_INTMASK);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	724
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	725 #if (ABB_SEMAPHORE_PROTECTION == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	726 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	727 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	728 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	729 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	730 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	731 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	732
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	733 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	734 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	735 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	736 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	737 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	738
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	739
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	740
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	741
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	742 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	743 /* ABB_sleep() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	744 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	745 /* This function disables the DCDC and returns to PAGE 0. It stops then */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	746 /* the 13MHz clock in ABB. A wait loop s required to allow */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	747 /* first slow access to ABB clock register. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	748 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	749 /* WARNING !! : this function must not be protected by semaphore !! */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	750 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	751 /* Returns AFC value. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	752 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	753 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	754 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	755 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	756 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	757 SYS_UWORD32 afcout_index;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	758 volatile SYS_UWORD16 nb_it;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	759 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	760
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	761 // table for AFC allowed values during Sleep mode. First 5th elements
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	762 // are related to positive AFC values, last 5th to negative ones.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	763 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f};
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	764
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	765 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	766 SPI_Ready_for_RDWR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	767 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	768
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	769 // COMPUTATION AND PROGRAMMING OF AFC VALUE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	770 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	771 if(afc & 0x1000)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	772 afcout_index = ((afc + 512)>>10) + 1;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	773 else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	774 afcout_index = (afc + 512)>>10;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	775
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	776 if (sleep_performed == FRAME_STOP) // Big sleep
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	777 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	778 #if ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	779 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP ////////////////////////////
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	780 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	781
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	782 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	783 else // Deep sleep
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	784 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	785 #if(ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	786 // SELECTION OF AFC TEST MODE FOR OMEGA
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	787 //---------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	788 // This test configuration allows access on the AFCOUT register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	789 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	790
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	791 // This transmission enables OMEGA test register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	792 ABB_WriteRegister(TAPCTRL, 0x01);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	793
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	794 // This transmission selects OMEGA test instruction.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	795 ABB_WriteRegister(TAPREG, AFCTEST);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	796
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	797 // Set AFCOUT to 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	798 ABB_WriteRegister(AFCOUT, 0x00 >> 6);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	799
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	800 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	801
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	802 #elif (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	803 // This configuration allows access on the AFCOUT register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	804 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	805
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	806 // Read AFCCTLADD value and enable USP access to AFCOUT register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	807 reg_val = (ABB_ReadRegister(AFCCTLADD) \| 0x04);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	808
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	809 ABB_WriteRegister(AFCCTLADD, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	810
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	811 // Set AFCOUT to 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	812 ABB_WriteRegister(AFCOUT, 0x00);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	813
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	814 #if ENABLE_BACKUP_BATTERY
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	815 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	816 reg_val = ABB_ReadRegister(BCICONF) & 0x039f;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	817
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	818 ABB_WriteRegister(BCICONF, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	819 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	820
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	821 // Disable the ABB test mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	822 ABB_WriteRegister(TAPCTRL, 0x00);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	823
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	824 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	825
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	826 // Read BCICTL1 value and cut the measurement bridge of MB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	827 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	828
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	829 ABB_WriteRegister(BCICTL1, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	830 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	831
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	832 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	833 // in Syren during sleep mode. BB charge stays enabled
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	834 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	835 // change the register page in IOTA for usp to pg1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	836
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	837 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	838
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	839 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	840 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	841
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	842 // switch off MADC, AFC, AUXDAC, VOICE.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	843 ABB_WriteRegister(TOGBR1, 0x155);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	844
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	845 // Switch off Analog supply LDO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	846 //-----------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	847 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	848 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	849
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	850 // Read VRPCCTL3 register value and switch off VR3.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	851 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	852
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	853 ABB_WriteRegister(VRPCCTRL3, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	854
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	855 #elif (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	856 // Read VRPCSTS register value and extract status of meaningfull inputs.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	857 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	858
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	859 if (reg_val == 0x30)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	860 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	861 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	862 ABB_WriteRegister(VRPCDEV, 0x02);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	863 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	864
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	865 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read".
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	866 ABB_WriteRegister(0x0000 \| 0x0001, 0x0000);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	867
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	868 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	869 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	870 // start the SLPDLY counter in order to switch the ABB in sleep mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	871 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	872 // set Syren sleep bit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	873 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	874 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read".
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	875 ABB_WriteRegister(0x0000 \| 0x0001, 0x0000);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	876 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	877 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	878
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	879 // Switch to low frequency clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	880 ABB_stop_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	881 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	882
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	883 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	884 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	885 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	886 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	887
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	888 #if (OP_L1_STANDALONE == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	889 #if (CHIPSET == 12)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	890 // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	891 // workaround to set APLL_DIV_CLK( internal PU) at high level
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	892 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	893 // (SYS_UWORD16) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	894 // (SYS_UWORD16) (0xFFFEF030)= 0x10;// DPLL mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	895 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	896 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	897 return(Afcout_T[afcout_index]);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	898 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	899
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	900
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	901 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	902 /* ABB_wakeup() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	903 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	904 /* This function sets the 13MHz clock working in ABB. A wait loop */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	905 /* is required to allow first slow access to ABB clock register. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	906 /* Then it re-enables DCDC and returns to PAGE 0. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	907 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	908 /* WARNING !! : this function must not be protected by semaphore !! */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	909 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	910 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	911 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	912 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	913 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	914 SYS_UWORD16 reg_val;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	915
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	916 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	917 SPI_Ready_for_RDWR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	918 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	919
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	920 if (sleep_performed == FRAME_STOP) // Big sleep
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	921 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	922 #if ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	923 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP ////////////////////////////
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	924 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	925 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	926 else // Deep sleep
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	927 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	928 #if (OP_L1_STANDALONE == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	929 #if (CHIPSET == 12)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	930 // restore context from
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	931 // workaround to set APLL_DIV_CLK( internal PU) at high level
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	932 // by default APLL_DIV_CLK is low pulling 80uA on VRIO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	933 // (SYS_UWORD16) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	934 // (SYS_UWORD16) (0xFFFEF030)= 0x00;// DPLL mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	935 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	936 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	937
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	938 // Restitutes 13MHZ Clock to ABB
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	939 ABB_free_13M();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	940
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	941 // Switch ON Analog supply LDO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	942 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	943 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	944
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	945 // Read VRPCCTL3 register value and switch on VR3.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	946 reg_val = ABB_ReadRegister(VRPCCTRL3) \| 0x020;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	947
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	948 ABB_WriteRegister(VRPCCTRL3, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	949 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	950 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	951
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	952 // This transmission switches on MADC, AFC.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	953 ABB_WriteRegister(TOGBR1, 0x280);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	954
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	955 // This transmission sets the AUXAFC2.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	956 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	957
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	958 // This transmission sets the AUXAFC1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	959 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	960
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	961 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	962 // Remove AFC test mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	963 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	964
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	965 // This transmission select Omega test instruction.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	966 ABB_WriteRegister(TAPREG, TSPTEST1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	967
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	968 // Disable test mode selection
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	969 // This transmission disables Omega test register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	970 ABB_WriteRegister(TAPCTRL, 0x00 >> 6);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	971
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	972 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	973
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	974 #elif (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	975 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	976
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	977 // Read AFCCTLADD register value and disable USP access to AFCOUT register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	978 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	979
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	980 ABB_WriteRegister(AFCCTLADD, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	981
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	982 #if ENABLE_BACKUP_BATTERY
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	983 // Read BCICONF register value and enable BB measurement bridge enable BB charge.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	984 reg_val = ABB_ReadRegister(BCICONF) \| 0x0060;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	985
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	986 ABB_WriteRegister(BCICONF, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	987 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	988
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	989
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	990 /* *************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	991 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	992 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	993 ABB_WriteRegister(VRPCCFG, (SLPDLY \| reg_val));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	994
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	995 // Enable the ABB test mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	996 ABB_WriteRegister(TAPCTRL, 0x01);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	997 ABB_WriteRegister(TAPREG, TSPEN);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	998 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	999
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1000 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1001 reg_val = ABB_ReadRegister(BCICTL1) \| 0x0001;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1002
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1003 ABB_WriteRegister(BCICTL1, reg_val);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1004 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1005
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1006 #if (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1007
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1008 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1009
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1010 /* *************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1011 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1012 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1013 ABB_WriteRegister(VRPCCFG, (SLPDLY \| reg_val));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1014
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1015 /* ********************** SELECTION OF TEST MODE FOR ABB=3 ***************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1016 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1017 /* ****************************************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1018
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1019 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1020 // This transmission enables IOTA test register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1021
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1022 ABB_WriteRegister(TAPREG, TSPEN);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1023 // This transmission select IOTA test instruction
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1024 // This transmission select IOTA test instruction
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1025 /**************************************************************************************************** */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1026
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1027 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1028 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1029 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1030
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1031 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1032 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1033 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1034 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1035 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1036
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1037 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1038 /* ABB_wa_VRPC() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1039 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1040 /* This function initializes the VRPCCTRL1 or VRPCSIM register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1041 /* according to the ABB used. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1042 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1043 /------------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1044 void ABB_wa_VRPC(SYS_UWORD16 value)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1045 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1046 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1047
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1048 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1049 SPI_Ready_for_WR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1050 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1051
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1052 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1053
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1054 // check if the semaphore has been correctly created and try to obtain it.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1055 // if the semaphore cannot be obtained, the task is suspended and then resumed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1056 // as soon as the semaphore is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1057 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1058 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1059 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1060 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1061 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1062
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1063 ABB_SetPage(PAGE1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1064
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1065 #if (ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1066 // This transmission initializes the VRPCCTL1 register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1067 ABB_WriteRegister(VRPCCTRL1, value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1068
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1069 #elif (ANLG_FAM == 2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1070 // This transmission initializes the VRPCSIM register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1071 ABB_WriteRegister(VRPCSIM, value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1072
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1073 #elif (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1074 // This transmission initializes the VRPCSIMR register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1075 ABB_WriteRegister(VRPCSIMR, value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1076
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1077 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1078
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1079 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1080
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1081 #if ((ABB_SEMAPHORE_PROTECTION == 1) \|\| (ABB_SEMAPHORE_PROTECTION == 2) \|\| (ABB_SEMAPHORE_PROTECTION == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1082 // release the semaphore only if it has correctly been created.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1083 if(&abb_sem != 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1084 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1085 NU_Release_Semaphore(&abb_sem);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1086 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1087 #endif // ABB_SEMAPHORE_PROTECTION
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1088
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1089 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1090 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1091 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1092 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1093 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1094
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1095
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1096 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1097 /* ABB_Write_Uplink_Data() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1098 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1099 /* This function uses the SPI to write to ABB uplink buffer. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1100 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1101 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1102 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1103 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1104 SYS_UWORD8 i;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1105 volatile SYS_UWORD16 status;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1106
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1107 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1108 SPI_Ready_for_WR
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1109 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1110
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1111 // Select Page 0 for TOGBR2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1112 ABB_SetPage(PAGE0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1113
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1114 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1115 ABB_WriteRegister(TOGBR2, 0x10);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1116
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1117 // Clear, assuming that it works like IBUFPTR of Vega
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1118 ABB_WriteRegister(TOGBR2, 0x0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1119
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1120 // Write the ramp data
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1121 for (i=0;i<16;i++)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1122 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1123
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1124 // Stop the SPI clock
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1125 #ifdef SPI_CLK_LOW_POWER
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1126 SPI_CLK_DISABLE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1127 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1128 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1129
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1130 //////////////////////// IDEV-INLO integration of sleep mode for Syren ///////////////////////////////////////
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1131
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1132 #if (ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1133
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1134 // Syren Sleep configuration function --------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1135 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1136 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1137 volatile SYS_UWORD16 status,sl_ldo_stat;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1138
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1139 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1140 // change the register page in ABB for usp to pg1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1141
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1142 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1143
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1144 sl_ldo_stat = ((sleep_type<<9\|bg_select<<8) & 0x0374);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1145
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1146 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1147
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1148 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1149 // change the register page in ABB for usp to pg0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1150 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1151 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1152
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1153
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1154 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1155 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1156 /* ABB_Power_Off() */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1157 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1158 /* This function uses the SPI to switch off the ABB. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1159 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1160 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1161 void ABB_Power_Off(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1162 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1163 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks).
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1164 NU_Sleep (30);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1165
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1166 // Wait also until <ON/OFF> key is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1167 // This is needed to avoid, if the power key is pressed for a long time, to switch
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1168 // ON-switch OFF the mobile, until the power key is released.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1169 #if((ANLG_FAM == 1) \|\| (ANLG_FAM == 2))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1170 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1171 #elif(ANLG_FAM == 3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1172 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1173 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1174
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1175 NU_Sleep (1); }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1176
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1177 BZ_KeyBeep_OFF();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1178
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1179 #if(ANLG_FAM == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1180 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1181 #elif((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1182 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1183 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1184 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1185 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1186
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1187
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1188

FreeCalypso > hg > fc-selenite

annotate src/cs/drivers/drv_core/abb/abb.c @ 147:0d96c28dedb1