annotate components/libsys_ir @ 192:4f40ae165be4

abb.c & init.c: sync with Magnetite for Luna additions These Luna target-specific additions are conditionalized on CONFIG_TARGET_LUNA, a C preprocessor symbol that will never be defined in Selenite, hence this change has exactly zero impact on FC Selenite. However, they are being pulled in as a sync in order to keep the diff between Magnetite and Selenite to a minimum; keeping this diff to a minimum increases our opportunities for possible evolution of future FC firmwares.
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 23 May 2020 07:03:46 +0000
parents 727aad1c308f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
87
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 # gcc-only component: libsys (selective libc replacement) for IRAM
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 ASMFLAGS=-mthumb-interwork
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 CPPFLAGS=
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 SRCDIR=$SRC/libsys
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7
727aad1c308f components/libsys_{fl,ir}: created
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 asm_file $SRCDIR/bzero.S