FreeCalypso > hg > fc-selenite

annotate src/cs/layer1/cfile/l1_small_asm.S @ 104:82ae724ca0d7

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OSL reconstruction fixed to support memory supervision
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 23 Jul 2018 01:47:29 +0000
parents a2052ac75672
children d43dadd91383
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a2052ac75672 l1_small_asm.S: import from Citrine
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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2 * Assembly code extracted out of TI's l1_small.c
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3 *
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4 * This code is correct ONLY for CHIPSET 10 or 11 as currently used
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5 * by FreeCalypso; see TI's original code for what changes would be
a2052ac75672 l1_small_asm.S: import from Citrine
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6 * needed to support other CHIPSETs.
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7 */
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8
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9 .text
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10 .code 32
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11
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12 /*-------------------------------------------------------*/
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13 /* _GSM_Small_Sleep */
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14 /* (formerly INT_Small_Sleep) */
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15 /*-------------------------------------------------------*/
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16 /* */
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17 /* Description: small sleep */
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18 /* ------------ */
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19 /* Called by TCT_Schedule main loop of Nucleus */
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20 /*-------------------------------------------------------*/
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21
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22 #define SMALL_SLEEP 0x01
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23 #define ALL_SLEEP 0x04
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24 #define PWR_MNGT 0x01
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25
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26 .globl _GSM_Small_Sleep
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27 _GSM_Small_Sleep:
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28
a2052ac75672 l1_small_asm.S: import from Citrine
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29 ldr r0,Switch
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30 ldr r0,[r0]
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31 ldrb r1,[r0]
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32 cmp r1,#PWR_MNGT
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33 bne TCT_Schedule_Loop
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34
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35 ldr r0,Mode
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36 ldr r0,[r0]
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37 ldrb r1,[r0]
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38 cmp r1,#SMALL_SLEEP
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39 beq Small_sleep_ok
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40 cmp r1,#ALL_SLEEP
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41 bne TCT_Schedule_Loop
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42
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43 Small_sleep_ok:
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44
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45 // *****************************************************
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46 //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register
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47 // (Cf BUG_1278)
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48
a2052ac75672 l1_small_asm.S: import from Citrine
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49 ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address
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50 ldrh r1,[r0] @ take the current value of the register
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51 orr r1,r1,#0x1000 @ reset the bit
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52 strh r1,[r0] @ store the result
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53
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54 ldr r0,addrCLKM @ pick up CLKM clock register address
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55 ldrh r1,[r0] @ take the current value of the register
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56 bic r1,r1,#1 @ disable ARM clock
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57 strh r1,[r0]
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58
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59 B TCT_Schedule_Loop @ Return to TCT_Schedule main loop
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60
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61 addrCLKM: .word 0xfffffd00 @ CLKM clock register address
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62
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63 Mode: .word mode_authorized
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64 Switch: .word switch_PWR_MNGT