FreeCalypso > hg > fc-selenite

annotate src/cs/system/main/gcc/exceptions.S @ 104:82ae724ca0d7

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
OSL reconstruction fixed to support memory supervision
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 23 Jul 2018 01:47:29 +0000
parents 92fde62400ef
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
78
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This module contains ARM exception handlers which used to be
83
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
3 * in chipsetsw/system/Main/int.s in TI's original version.
78
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 */
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 .text
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 .code 32
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 @ layout of xdump buffer:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 @ struct xdump_s {
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 @ long registers[16] // svc mode registers
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 @ long cpsr // svc mode CPSR
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 @ long exception // magic word + index of vector taken
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 @ long stack[20] // bottom 20 words of usr mode stack
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 @ }
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 .globl _arm_undefined
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 _arm_undefined:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 @ store r12 for Xdump_buffer pointer, r11 for index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 stmfd r13!,{r11,r12}
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 mov r11,#1
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 b save_regs
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 .globl _arm_swi
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 _arm_swi:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 @ store r12 for Xdump_buffer pointer, r11 for index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 stmfd r13!,{r11,r12}
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 mov r11,#2
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 b save_regs
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 .globl _arm_abort_prefetch
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 _arm_abort_prefetch:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 @ store r12 for Xdump_buffer pointer, r11 for index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 stmfd r13!,{r11,r12}
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 mov r11,#3
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 b save_regs
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 .globl _arm_abort_data
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 _arm_abort_data:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 @ store r12 for Xdump_buffer pointer, r11 for index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 stmfd r13!,{r11,r12}
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 mov r11,#4
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 b save_regs
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 .globl _arm_reserved
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 _arm_reserved:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 ldr r13,=_Except_Stack_SP @ mode unknown
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 @ store r12 for Xdump_buffer pointer, r11 for index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 stmfd r13!,{r11,r12}
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 mov r11,#5
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 b save_regs
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 save_regs:
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 ldr r12,=xdump_buffer
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 str r14,[r12,#4*15] @ save r14_abt (original PC) into r15 slot
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 stmia r12,{r0-r10} @ save unbanked registers (except r11 and r12)
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 ldmfd r13!,{r0,r1} @ get original r11 and r12
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 str r0,[r12,#4*11] @ save original r11
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 str r1,[r12,#4*12] @ save original r12
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61 mrs r0,spsr @ get original psr
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62 str r0,[r12,#4*16] @ save original cpsr
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 mrs r1,cpsr @ save mode psr
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 bic r2,r1,#0x1f @ psr with mode bits cleared
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 and r0,r0,#0x1f @ get original mode bits
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 add r0,r0,r2
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 msr cpsr,r0 @ move to pre-exception mode
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 str r13,[r12,#4*13] @ save original SP
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 str r14,[r12,#4*14] @ save original LR
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 msr cpsr,r1 @ restore mode psr
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 @ r11 has original index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 orr r10,r11,#0xDE<<24 @ r10 = 0xDEAD0000 + index of vector taken
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 orr r10,r10,#0xAD<<16
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 str r10,[r12,#4*17] @ save magic + index
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 mov r0,r11 @ put index into 1st argument
95ef11e76c5b src/cs/system/main/gcc: asm code pieced from Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80 b dar_exception
83
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
81
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
82 @ the second part
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
83
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
84 /*
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
85 * For the SP-in-RAM validity check, we use the following simplification:
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
86 * it doesn't really matter what the actual IRAM and XRAM sizes are on
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
87 * any given target, as the address decoder hooked up to the ARM7TDMI core
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
88 * always decodes the full 8 MiB address range for each, causing the
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
89 * actual memories to be aliased multiple times in those two ranges.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
90 * Furthermore, the XRAM address range falls right after the IRAM one,
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
91 * thus we can get away with only a single range check.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
92 */
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
93
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
94 #define RAM_LOW 0x00800000
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
95 #define RAM_HIGH 0x01800000
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
96
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
97 #define XDUMP_STACK_SIZE 20
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
98
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
99 .globl exception
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
100 exception:
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
101 ldr r12,=xdump_buffer
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
102 ldr r11,[r12,#4*13] @ get svc mode r13
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
103 add r12,r12,#4*18 @ base of stack buffer
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
104
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
105 @ check if svc r13(sp) is within internal/external RAM.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
106 @ It *could* be invalid.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
107 cmp r11,#RAM_LOW
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
108 blt nostack
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
109 mov r0,#RAM_HIGH
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
110 sub r0,r0,#XDUMP_STACK_SIZE
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
111 cmp r11,r0
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
112 bge nostack
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
113
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
114 stack_range:
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
115 ldmfd r11!,{r0-r9} @ copy ten stack words..
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
116 stmia r12!,{r0-r9}
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
117 ldmfd r11!,{r0-r9} @ copy ten stack words..
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
118 stmia r12!,{r0-r9}
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
119
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
120 nostack:
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
121 @ we're finished saving all state.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
122 @ Now execute C code for more flexibility.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
123 @ set up a stack for this C call
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
124 ldr sp,=_Stack_segment_end
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
diff changeset
125 b dar_reset