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annotate src/g23m-gsm/alr2/alr_trc.c @ 158:8fe0cde2fd79

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doc/Compiling: update for SE J100 target and fc-host-tools-r10
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 17 Mar 2019 07:20:28 +0000
parents b4c81ea2d291
children
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1 /*
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2 +-----------------------------------------------------------------------------
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3 | Project : GSM-PS
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4 | Modul : ALR_TRC
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5 +-----------------------------------------------------------------------------
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6 | Copyright 2002 Texas Instruments Berlin, AG
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7 | All rights reserved.
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8 |
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9 | This file is confidential and a trade secret of Texas
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10 | Instruments Berlin, AG
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11 | The receipt of or possession of this file does not convey
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12 | any rights to reproduce or disclose its contents or to
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13 | manufacture, use, or sell anything it may describe, in
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14 | whole, or in part, without the specific written consent of
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15 | Texas Instruments Berlin, AG.
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16 +-----------------------------------------------------------------------------
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17 | Purpose : This Modul defines functions for the offline trace
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18 +-----------------------------------------------------------------------------
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19 */
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20
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21 #ifndef ALR_TRC_C
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22 #define ALR_TRC_C
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23
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24 #define ENTITY_PL
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26 /*==== INCLUDES ===================================================*/
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27 #include <string.h>
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28 #include <stdlib.h>
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29 #include <ctype.h>
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30 #include "typedefs.h"
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31 #include "pconst.cdg"
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32 #include "mconst.cdg"
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33 #include "message.h"
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34 #include "ccdapi.h"
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35 #include "vsi.h"
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36 #include "custom.h"
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37 #include "gsm.h"
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38 #include "prim.h"
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39 #include "cnf_alr.h"
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40 #include "mon_alr.h"
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41 #include "pei.h"
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42 #include "tok.h"
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43 #include "pcm.h"
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44
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45 #ifdef GPRS
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46 #include "alr_gprs.h"
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47 #endif
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48
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49 #include "alr.h"
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50
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51 #if defined (ALR_TRACE_ENABLED)
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52 /*
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53 * The ALR Trace is a cyclic buffer for
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54 * debugging ALR problems.
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55 *
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56 * The buffer will be initialized at startup and will
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57 * be filled by the function alr_trc_dl_trace() until it is full.
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58 * The size of the buffer is ALR_TRC_SIZE.
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59 *
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60 * The content is
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61 *
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62 * actual_channel
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63 * State
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64 * sysclock
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65 * L2 data
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66 *
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67 * During IDLE mode (triggered by RX_PERIODIC_IND in ALR/TIL_main.c)
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68 * an output is written to the _PL.dbg (ALR_TRC_MAX_READED traces each trigger)
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69 */
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70
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71 /* prototypes */
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72 void alr_trc_clear (void);
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73 #define ALR_TRC_SIZE 90
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74 #define ALR_TRC_MAX_READED 8
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75
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76 #if (((ALR_TRC_SIZE-1) & (~ALR_TRC_SIZE)) == (ALR_TRC_SIZE-1))
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77 #define POWER_OF_2
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78 #pragma message("ALR_TRC_SIZE is power of 2")
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79 #else
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80 #pragma message("ALR_TRC_SIZE is NOT power of 2")
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81 #endif
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82
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83 typedef struct
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84 {
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85 UCHAR event;
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86 UCHAR state;
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87 UCHAR actual_channel;
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88 USHORT sysclock;
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89 UCHAR data [ALR_TRC_DATA_SIZE];
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90 } T_IDLE_TRACE_DATA;
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91
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92 T_IDLE_TRACE_DATA alr_csIDLE_Trace_buffer [ALR_TRC_SIZE];
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93 USHORT alr_csIDLE_Trace_index = 0;
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94 USHORT alr_csIDLE_Trace_read_index = 0;
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95
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96 static T_HANDLE sem_ALR_TRC;
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97
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98 #define ENTER_CRITICAL_SECTION(sem) if (alr_trc_enter_critical_section(sem))return;
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99 #define LEAVE_CRITICAL_SECTION(sem) if (alr_trc_leave_critical_section(sem))return;
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100
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101
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102 /*
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103 +-----------------------------------------------------------------------------+
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104 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
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105 | STATE : code ROUTINE : alr_trc_semaphore_err |
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106 +-----------------------------------------------------------------------------+
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107
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108 PURPOSE : Handles semaphore error situation
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109
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110 */
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111
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112 static void alr_trc_semaphore_err (void)
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113 {
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114 static UCHAR out = 0;
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115 if (!out)
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116 {
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117 out = 1;
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118 vsi_o_ttrace(VSI_CALLER TC_EVENT, "semaphore error");
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 }//endfunc alr_trc_dl_trace_cs_err
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 +-----------------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 | STATE : code ROUTINE : alr_trc_enter_critical_section |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 +-----------------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 PURPOSE : Enters critical section
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 static int alr_trc_enter_critical_section (T_HANDLE sem)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 if (vsi_s_get (VSI_CALLER sem) NEQ VSI_OK)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 alr_trc_semaphore_err();
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 return -1;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 return 0;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 }//endfunc alr_trc_enter_critical_section
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 +-----------------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 | STATE : code ROUTINE : alr_trc_leave_critical_section |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 +-----------------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 PURPOSE : Leaves critical section
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 static int alr_trc_leave_critical_section (T_HANDLE sem)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 if (vsi_s_release (VSI_CALLER sem) NEQ VSI_OK)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 alr_trc_semaphore_err();
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 return -1;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 return 0;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 }//endfunc alr_trc_leave_critical_section
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 | STATE : code ROUTINE : alr_trc_init |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 PURPOSE : Init tracing
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 void alr_trc_init (void)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 sem_ALR_TRC = vsi_s_open (VSI_CALLER "ALR_IDLE_TRACE",1);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 if (sem_ALR_TRC NEQ VSI_ERROR)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 alr_trc_clear ();
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 vsi_o_ttrace(VSI_CALLER TC_EVENT, "can´t open semaphore \"ALR_IDLE_TRACE\"");
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 | STATE : code ROUTINE : alr_trc_exit |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 PURPOSE : Close tracing
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 void alr_trc_exit (void)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 if (sem_ALR_TRC NEQ VSI_ERROR)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 vsi_s_close (VSI_CALLER sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 | STATE : code ROUTINE : alr_trc_clear |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 PURPOSE : Clears trace index
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 void alr_trc_clear (void)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 alr_csIDLE_Trace_index = alr_csIDLE_Trace_read_index = 0;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 vsi_o_ttrace(VSI_CALLER TC_EVENT, "IDLE_Trace_index reseted");
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 #if 0
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 static void alr_trc_sleep_mode (void)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 static UCHAR sleep_mode_disabled = FALSE;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 if (!sleep_mode_disabled)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 #define NO_SLEEP 0
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 #define ARMIO_CLK 0x0001
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 #define UWIRE_CLK 0x0020
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 #define SIM_CLK 0x0040
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 #define UART_CLK 0x0400
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 #if defined (_TARGET_)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 #if !defined( GPRS )
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 power_down_config(NO_SLEEP, ARMIO_CLK | UWIRE_CLK | SIM_CLK | UART_CLK);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 #endif
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 #endif /* _TARGET_ */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 sleep_mode_disabled = TRUE;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 }//endfunc alr_trc_sleep_mode
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 #endif /* 0|1 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 | STATE : code ROUTINE : alr_trc_store |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 PURPOSE : Fill in a trace.
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 void alr_trc_store (UCHAR event, UCHAR actual_channel, UCHAR state, void* data)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 T_IDLE_TRACE_DATA* trace_data;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 USHORT write_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 USHORT length;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 T_TIME sysClock;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 #if 0
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 USHORT semCount;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 if (vsi_s_status (VSI_CALLER sem_ALR_TRC, &semCount) NEQ VSI_OK)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 alr_trc_semaphore_err();
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 return;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 if (semCount EQ 0)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 vsi_o_ttrace(VSI_CALLER TC_EVENT, "semCount == 0");
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 return;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 #endif /* 0|1 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 #if defined(POWER_OF_2)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 write_index = (alr_csIDLE_Trace_index + 1) & (ALR_TRC_SIZE - 1); /* if ALR_TRC_SIZE power of 2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 #else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 write_index = (alr_csIDLE_Trace_index + 1) % ALR_TRC_SIZE; /* if ALR_TRC_SIZE not power of 2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 #endif /* POWER_OF_2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 if (write_index NEQ alr_csIDLE_Trace_read_index)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 {/* buffer is not full */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 trace_data = &alr_csIDLE_Trace_buffer[alr_csIDLE_Trace_index];
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 trace_data->event = event;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 if (actual_channel >= ALR_TRC_CH_UNKNOWN)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 trace_data->actual_channel = ALR_TRC_CH_UNKNOWN;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 trace_data->actual_channel = actual_channel;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 trace_data->state = state;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 vsi_t_time (VSI_CALLER &sysClock);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 trace_data->sysclock = (USHORT)sysClock;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 if (event EQ ALR_TRC_DOWNLINK OR event EQ ALR_TRC_UPLINK)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 length = 23;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 length = ALR_TRC_DATA_SIZE;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 if (event EQ ALR_TRC_STRING)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 strncpy ((char*)trace_data->data, (char*)data, length);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 memcpy (trace_data->data, (UCHAR*)data, length);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 alr_csIDLE_Trace_index = write_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 }/* endif buffer is not full */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 }/* endfunc alr_trc_store */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 /*
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 | PROJECT : GSM-PS (6147) MODULE : ALT_TRC |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 | STATE : code ROUTINE : alr_trc_read |
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 +--------------------------------------------------------------------+
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 PURPOSE : Read and output stored trace.
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 void alr_trc_read_all (void)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 USHORT write_index, read_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 write_index = alr_csIDLE_Trace_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 read_index = alr_csIDLE_Trace_read_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 while (read_index NEQ write_index)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 alr_trc_read (20);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 vsi_t_sleep(VSI_CALLER 0);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 write_index = alr_csIDLE_Trace_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 read_index = alr_csIDLE_Trace_read_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 }/* endfunc alr_trc_dl_trace_read_all */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 static const char * ALR_TRC_CHANNEL[7] = { " ", "Ff", "Fh", "S4", "S8", "SA", "??" };
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 static const char * ALR_TRC_EVENTS[4] = { "UL", "DL", "Ev", "ev" };
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 void alr_trc_read (int count)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 T_IDLE_TRACE_DATA trace_data;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 USHORT write_index, read_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 static char buffer[ALR_TRC_DATA_SIZE*2+50];
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 UCHAR j, o, readed = 0;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 write_index = alr_csIDLE_Trace_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 read_index = alr_csIDLE_Trace_read_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 #if 0
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 if (read_index EQ write_index)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 alr_trc_sleep_mode ();
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 return;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 #endif /* 0|1 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 while (read_index NEQ write_index)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 trace_data = alr_csIDLE_Trace_buffer[read_index];
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 alr_csIDLE_Trace_buffer[read_index].sysclock = 0xffff; /* readed */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 alr_csIDLE_Trace_read_index++;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 #if defined(POWER_OF_2)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 alr_csIDLE_Trace_read_index&= (ALR_TRC_SIZE-1); /* if power of 2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 #else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 alr_csIDLE_Trace_read_index%= ALR_TRC_SIZE; /* if not power of 2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 #endif /* POWER_OF_2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 read_index = alr_csIDLE_Trace_read_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 sprintf (buffer, "[%03d]:%05d %d %s %s ",
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 #if defined(POWER_OF_2)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 (write_index - read_index) & (ALR_TRC_SIZE-1), /* if ALR_TRC_SIZE power of 2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 #else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 (ALR_TRC_SIZE + write_index - read_index) % ALR_TRC_SIZE, /* if ALR_TRC_SIZE not power of 2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 #endif /* POWER_OF_2 */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 trace_data.sysclock,
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 trace_data.state,
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 ALR_TRC_EVENTS[trace_data.event],
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 ALR_TRC_CHANNEL[trace_data.actual_channel]);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 o = strlen (buffer);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 switch (trace_data.event)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 case ALR_TRC_STRING:
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 strncpy (buffer+o, (char*)&trace_data.data[0], ALR_TRC_DATA_SIZE);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 buffer[o+ALR_TRC_DATA_SIZE] = 0;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 break;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 case ALR_TRC_DOWNLINK:
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 case ALR_TRC_UPLINK:
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 for (j=0;j<23;j++, o+=2)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 sprintf (buffer+o, "%02x", trace_data.data[j]);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 break;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 default:
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 for (j=0;j<ALR_TRC_DATA_SIZE;j++, o+=2)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 sprintf (buffer+o, "%02x", trace_data.data[j]);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 break;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 if (buffer[0])
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 vsi_o_ttrace(VSI_CALLER TC_EVENT, buffer);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 else
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 {
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 vsi_o_ttrace(VSI_CALLER TC_EVENT, "alr_trc_read() failed");
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 }
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 ENTER_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 write_index = (UCHAR)alr_csIDLE_Trace_index;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 LEAVE_CRITICAL_SECTION (sem_ALR_TRC);
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 if (++readed >= count)
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 break;
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 }/* endwhile */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 }//endfunc alr_trc_read */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 #else /* ALR_TRACE_ENABLED */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 #endif /* ALR_TRACE_ENABLED */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 #endif /* ALR_TRC_C */
b4c81ea2d291 src/g23m-gsm/alr2: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444