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annotate src/cs/layer1/dl1/dl1_com.c @ 61:935692f51b38

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src/g23m-gsm/alr2/alr.h: removed bogus extern to pass gcc compilation
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 19 Jul 2018 23:30:08 +0000
parents d2074d1102e0
children c7af699af1c4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0
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1 /*
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2 * This module contains the LISR and HISR glue functions for L1
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3 * which used to be in the dl1_com module in the Leonardo version.
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4 * The LoCosto source from which we got our L1 code no longer has a
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5 * dl1_com.c module, and the ISR glue functions in question have been
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6 * moved into csw-system/init_common/init.c - an incredibly messy C
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7 * module that is mostly devoted to LoCosto BSP initialization.
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8 *
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9 * The present C code has been extracted from LoCosto's init.c,
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10 * guided by the disassembly of dl1_com.obj from the Leonardo version.
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11 */
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12
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13 /* Include Files */
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14 #include <assert.h>
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15 #include <stdarg.h>
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16 #include <stdio.h>
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17 #include <stdlib.h>
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18 #include <string.h>
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19
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20 #include "nucleus.h"
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21
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22 #include "l1_types.h"
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23 #include "l1_confg.h"
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24 #include "l1_const.h"
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25
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26 #if TESTMODE
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27 #include "l1tm_defty.h"
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28 #endif // TESTMODE
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29
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30 #if (AUDIO_TASK == 1)
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31 #include "l1audio_const.h"
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32 #include "l1audio_cust.h"
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33 #include "l1audio_defty.h"
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34 #endif // AUDIO_TASK
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35
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36 #if (L1_GTT == 1)
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37 #include "l1gtt_const.h"
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38 #include "l1gtt_defty.h"
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39 #endif
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40
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41 #if (L1_MP3 == 1)
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42 #include "l1mp3_defty.h"
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43 #endif
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44
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45 #if (L1_MIDI == 1)
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46 #include "l1midi_defty.h"
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47 #endif
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48
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49 #if (L1_AAC == 1)
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50 #include "l1aac_defty.h"
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51 #endif
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52 #if (L1_DYN_DSP_DWNLD == 1)
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53 #include "l1_dyn_dwl_defty.h"
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54 #endif
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55
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56 #if (TRACE_TYPE == 4)
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57 #include "l1_defty.h"
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58 #endif
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59
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60 #include "armio.h"
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61 #include "timer.h"
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62
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63 #include "iq.h"
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64 #include "mem.h"
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65 #include "clkm.h"
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66 #include "inth.h"
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67
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68 /*
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69 * Timing monitor
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70 */
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71 #if (TRACE_TYPE == 4)
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72 extern T_L1A_L1S_COM l1a_l1s_com;
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73 extern T_L1S_GLOBAL l1s;
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74 UNSIGNED max_cpu, fn_max_cpu;
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75 unsigned short layer_1_sync_end_time;
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76 unsigned short max_cpu_flag;
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77 #if (DSP >= 38)
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78 // DSP CPU load measurement trace variables
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79 UWORD32 dsp_max_cpu_load_trace_array[4];
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80 UWORD32 dsp_max_cpu_load_idle_frame;
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81 unsigned short l1_dsp_cpu_load_trace_flag;
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82 #endif
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83 #endif
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84
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85 #if (L1_EXT_AUDIO_MGT == 1)
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86 NU_HISR EXT_AUDIO_MGT_hisr;
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87 char FAR ext_audio_mgt_hisr_stack[500];
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88 extern void Cust_ext_audio_mgt_hisr(void);
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89 #endif
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90
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91 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) ) // equivalent to an API_HISR flag
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92 extern void api_hisr(void);
47
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93 #ifdef __GNUC__
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94 #define SECTION_ATTR __attribute__ ((section ("API_HISR_stack")))
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95 #else
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96 #define SECTION_ATTR
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97 #pragma DATA_SECTION (API_HISR_stack,"API_HISR_stack");
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98 #endif
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99 char FAR API_HISR_stack[0x400] SECTION_ATTR;
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100 #undef SECTION_ATTR
0
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101 NU_HISR apiHISR;
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102 #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1)
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103
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104 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1)
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105 char FAR API_MODEM_HISR_stack[0x400]; // stack size to be tuned
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106 NU_HISR api_modemHISR;
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107 #endif // FF_L1_IT_DSP_USF
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108
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109 /*
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110 * HISR stack and semaphore needed by L1
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111 */
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112 #if (OP_L1_STANDALONE == 0)
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113 #define LAYER_1_SYNC_STACK_SIZE 4000 /* matching Leonardo version */
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114 unsigned char layer_1_sync_stack[LAYER_1_SYNC_STACK_SIZE];
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115 #else
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116 #if TESTMODE
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117 char FAR layer_1_sync_stack[2600 /*3600*/]; // Frame interrupt task stack for EVA3
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118 #else
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119 char FAR layer_1_sync_stack[1600 /* 2600 */]; // Frame interrupt task stack for EVA3
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120 #endif
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121 #endif /* OP_L1_STANDALONE */
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122
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123 NU_HISR layer_1_sync_HISR; // Frame interrupt task stack for EVA3
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124
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125 /* forward declaration */
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126 void layer_1_sync_HISR_entry (void);
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127
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128 /*
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129 * l1_create_ISR
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parents:
diff changeset
130 *
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 * Create L1 HISR. This function is called from l1_pei.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 void l1_create_ISR (void)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 {
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 STATUS status;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite
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parents:
diff changeset
138 // Fill the entire stack with the pattern 0xFE
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 memset (layer_1_sync_stack, 0xFE, LAYER_1_SYNC_STACK_SIZE);
b6a5e36de839 src/cs: initial import from Magnetite
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parents:
diff changeset
140 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 status = NU_Create_HISR (&layer_1_sync_HISR,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 "L1_HISR",
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 layer_1_sync_HISR_entry,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 0,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 layer_1_sync_stack,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 LAYER_1_SYNC_STACK_SIZE);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 #else
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 0,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 layer_1_sync_stack,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 sizeof(layer_1_sync_stack));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 #if (L1_EXT_AUDIO_MGT)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 // Create HISR for Ext MIDI activity
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 //==================================
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 status += NU_Create_HISR(&EXT_AUDIO_MGT_hisr,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 "H_EXT_AUDIO_MGT",
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 Cust_ext_audio_mgt_hisr,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 1,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 ext_audio_mgt_hisr_stack,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 sizeof(ext_audio_mgt_hisr_stack));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) ) // equivalent to an API_HISR flag
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 status += NU_Create_HISR(&apiHISR,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 "API_HISR",
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 api_hisr,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 1,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 API_HISR_stack,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 sizeof(API_HISR_stack));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) // equivalent to an API_MODEM_HISR flag
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 // Create HISR for USF DSP interrupt !!!!. This HISR needs
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 // to have the highest priority since the USF status needs
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 // to be known before the next block starts.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 //========================================================
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 status += NU_Create_HISR(&api_modemHISR,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 "MODEM",
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 api_modem_hisr,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 0,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 API_MODEM_HISR_stack,
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 sizeof(API_MODEM_HISR_stack));
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 assert (status == 0);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 }
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 /*
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 * The versions of TP_FrameIntHandler() and layer_1_sync_HISR_entry()
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 * in the TCS211 dl1_com.obj module contain CPU load measurement
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 * code. TI changed things for LoCosto, so we have to revert their
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 * changes and restore the TCS211 way.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 #if (TRACE_TYPE == 4)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 #define TIMER_RESET_VALUE (0xFFFF)
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parents:
diff changeset
200 #define TICKS_PER_TDMA (1875)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 /*-------------------------------------------------------*/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 /* TP_FrameIntHandler() Low Interrupt service routine */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 /*-------------------------------------------------------*/
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 /* Parameters : */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 /* Return : */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 /* Functionality : activate Hisr on each frame interrupt*/
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 /*-------------------------------------------------------*/
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 void TP_FrameIntHandler(void)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 {
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 #if (OP_L1_STANDALONE == 1)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 #if (TRACE_TYPE==1)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 if (trace_info.current_config->l1_dyn_trace & 1<<L1_DYN_TRACE_L1S_CPU_LOAD)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 {
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 TM_ResetTimer (2, 0xFFFF, 1, 0);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 TM_StartTimer (2);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 #if (TRACE_TYPE==6)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 TM_ResetTimer (2, 0xFFFF, 1, 0);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 TM_StartTimer (2);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 #if (TRACE_TYPE==7) /* CPU_LOAD */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 l1_cpu_load_start();
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 #else
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 #if (TRACE_TYPE == 4) && (TI_NUC_MONITOR != 1)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 TM_ResetTimer (2, TIMER_RESET_VALUE, 1, 0);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 TM_StartTimer (2);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 #if (TI_NUC_MONITOR == 1)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 /* Copy LISR buffer in Log buffer each end of HISR */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 ti_nuc_monitor_tdma_action();
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 #if WCP_PROF == 1
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 prf_LogFNSwitch(l1s.actual_time.fn_mod42432);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 #endif /* OP_L1_STANDALONE */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 NU_Activate_HISR(&layer_1_sync_HISR); /* Activate HISR interrupt */
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 #if (WCP_PROF == 1)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 #if (PRF_CALIBRATION == 1)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 NU_Activate_HISR(&prf_CalibrationHISR);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 /*
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 * layer_1_sync_HISR_entry
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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264 *
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265 * HISR associated to layer 1 sync.
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266 */
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267
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268 void layer_1_sync_HISR_entry (void)
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269 {
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270 /* automatic var for the CPU load measurement code below */
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271 #if (TRACE_TYPE == 4)
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272 unsigned long cpu;
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273 #endif
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274
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275 // Call Synchronous Layer1
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276 hisr();
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277
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278 /*
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279 * FreeCalypso: the following code has been reconstructed from
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280 * the disassembly of the TCS211 binary object; it was found to be
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281 * similar to the Trace_L1S_CPU_load() function in l1_trace.c
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282 * which appears to have been only for (TRACE_TYPE == 1) originally.
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283 */
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284 #if (TRACE_TYPE == 4)
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285 layer_1_sync_end_time = TIMER_RESET_VALUE - TM_ReadTimer(2);
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286
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287 cpu = (100 * layer_1_sync_end_time) / TICKS_PER_TDMA;
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288 if (cpu > max_cpu)
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289 {
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290 max_cpu=cpu;
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291 fn_max_cpu=l1s.actual_time.fn;
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292 max_cpu_flag = 1;
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293 /*
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294 * TCS211 object has this bogus code here:
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295
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296 if (some non-understood condition) {
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297 static int i;
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298 i++; // static var never used anywhere
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299 max_cpu_flag = 1;
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300 }
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301
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302 * Because this bogus code does not change the result,
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303 * I decided not to bother with reconstructing it.
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304 */
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305 }
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306
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307 if (((l1s.actual_time.fn%1326) == 0) && (max_cpu_flag == 0))
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308 max_cpu = 0;
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309 #endif
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310 }
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311
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312 /* the following stub functions live in the dl1_com module per TCS211 */
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313
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314 void rx_tch_data (API *data_address,
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315 UWORD8 channel_mode,
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316 UWORD8 blk_seq_number)
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317 {
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318 }
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319
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320 UWORD8 *tx_tch_data (void)
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321 {
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322 return(NULL);
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323 }