FreeCalypso > hg > fc-selenite
annotate src/cs/layer1/p_cfile/l1p_driv.c @ 111:97297555c71a
FFS dev.c flash device table reworked as described in TCS211-fw-arch
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 13 Oct 2018 16:32:07 +0000 |
parents | b6a5e36de839 |
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rev | line source |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1P_DRIVE.C |
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4 * |
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5 * Filename l1p_driv.c |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 #define L1P_DRIVE_C |
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11 |
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12 #include "l1_macro.h" |
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13 #include "l1_confg.h" |
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14 |
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15 #if L1_GPRS |
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16 #if (CODE_VERSION == SIMULATION) |
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17 #include <string.h> |
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18 #include "l1_types.h" |
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19 #include "sys_types.h" |
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20 #include "l1_const.h" |
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21 #include "l1_time.h" |
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22 #if TESTMODE |
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23 #include "l1tm_defty.h" |
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24 #endif |
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25 #if (AUDIO_TASK == 1) |
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26 #include "l1audio_const.h" |
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27 #include "l1audio_cust.h" |
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28 #include "l1audio_defty.h" |
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29 #endif |
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30 #if (L1_GTT == 1) |
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31 #include "l1gtt_const.h" |
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32 #include "l1gtt_defty.h" |
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33 #endif |
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34 #if (L1_MP3 == 1) |
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35 #include "l1mp3_defty.h" |
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36 #endif |
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37 #if (L1_MIDI == 1) |
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38 #include "l1midi_defty.h" |
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39 #endif |
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40 #include "l1_defty.h" |
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41 #include "l1_varex.h" |
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42 #include "cust_os.h" |
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43 #include "l1_msgty.h" |
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44 #if L2_L3_SIMUL |
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45 #include "hw_debug.h" |
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46 #endif |
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47 |
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48 #include "l1p_cons.h" |
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49 #include "l1p_msgt.h" |
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50 #include "l1p_deft.h" |
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51 #include "l1p_vare.h" |
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52 #include "l1p_tabs.h" |
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53 |
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54 #include "sim_cons.h" |
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55 #include "sim_def.h" |
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56 extern T_hw FAR hw; |
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57 #include "l1_proto.h" |
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58 |
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59 #else |
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60 |
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61 #include <string.h> |
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62 #include "l1_types.h" |
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63 #include "sys_types.h" |
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64 #include "l1_const.h" |
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65 #include "l1_time.h" |
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66 |
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67 #if TESTMODE |
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68 #include "l1tm_defty.h" |
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69 #endif |
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70 #if (AUDIO_TASK == 1) |
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71 #include "l1audio_const.h" |
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72 #include "l1audio_cust.h" |
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73 #include "l1audio_defty.h" |
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74 #endif |
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75 #if (L1_GTT == 1) |
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76 #include "l1gtt_const.h" |
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77 #include "l1gtt_defty.h" |
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78 #endif |
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79 #if (L1_MP3 == 1) |
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80 #include "l1mp3_defty.h" |
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81 #endif |
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82 #if (L1_MIDI == 1) |
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83 #include "l1midi_defty.h" |
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84 #endif |
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85 #include "l1_defty.h" |
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86 #include "l1_varex.h" |
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87 #include "cust_os.h" |
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88 #include "l1_msgty.h" |
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89 #if L2_L3_SIMUL |
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90 #include "hw_debug.h" |
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91 #endif |
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92 |
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93 #include "l1p_cons.h" |
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94 #include "l1p_msgt.h" |
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95 #include "l1p_deft.h" |
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96 #include "l1p_vare.h" |
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97 #include "l1p_tabs.h" |
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98 |
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99 #include "l1_proto.h" |
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100 #include "tpudrv.h" |
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101 |
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102 #endif |
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103 |
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104 #if(RF_FAM == 61) |
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105 #include "l1_rf61.h" |
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106 #include "tpudrv61.h" |
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107 #include "l1_ctl.h" |
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108 #endif |
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109 |
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110 /*-------------------------------------------------------*/ |
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111 /* Prototypes of external functions used in this file. */ |
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112 /*-------------------------------------------------------*/ |
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113 void l1dmacro_synchro (UWORD32 when, UWORD32 value); |
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114 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time); |
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115 void l1dmacro_afc (UWORD16 afc_value, UWORD8 win_id); |
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116 |
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117 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61) ) |
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118 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq |
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119 #if(REL99 && FF_PRF) |
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120 ,UWORD8 number_uplink_timeslot |
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121 #endif |
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122 ); |
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123 #endif |
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124 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq); |
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125 |
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126 BOOL l1ps_swap_iq_ul (UWORD16 radio_freq); |
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127 BOOL l1ps_swap_iq_dl (UWORD16 radio_freq); |
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128 #if (L1_MADC_ON == 1) |
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129 #if (RF_FAM == 61) |
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130 void l1pdmacro_rx_up (UWORD16 radio_freq,UWORD8 adc_active, UWORD8 csf_filter_choice |
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131 #if (NEW_SNR_THRESHOLD == 1) |
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132 ,UWORD8 saic_flag |
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133 #endif /* NEW_SNR_THRESHOLD == 1*/ |
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134 ); |
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135 #endif |
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136 #else /* RF_FAM == 61*/ |
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137 void l1pdmacro_rx_up (UWORD16 radio_freq); |
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138 #endif |
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139 void l1pdmacro_rx_down (UWORD16 radio_freq, UWORD8 num_rx, BOOL rx_done_flag); |
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140 void l1pdmacro_tx_up (UWORD16 radio_freq); |
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141 void l1pdmacro_tx_down (UWORD16 radio_freq, WORD16 time, BOOL tx_flag, UWORD8 timing_advance,UWORD8 adc_active); |
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142 void l1pdmacro_tx_synth(UWORD16 radio_freq); |
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143 void l1pdmacro_anchor (WORD16 time); |
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144 |
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145 void l1dmacro_rx_synth(UWORD16 radio_freq); |
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146 void l1dmacro_agc(UWORD16 radio_freq, WORD8 agc_value, UWORD8 lna_off |
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147 #if (RF_FAM == 61) |
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148 ,UWORD8 if_ctl |
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149 #endif |
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150 ); |
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151 #if (CODE_VERSION == SIMULATION) |
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152 void l1dmacro_rx_ms (UWORD16 arfcn, BOOL rxnb_select); |
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153 #else |
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154 #if (L1_MADC_ON == 1) |
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155 #if (RF_FAM == 61) |
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156 void l1dmacro_rx_ms (UWORD16 arfcn,UWORD8 adc_active); |
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157 #endif |
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158 #else |
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159 void l1dmacro_rx_ms (UWORD16 arfcn); |
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160 #endif |
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161 #endif |
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162 void l1pdmacro_it_dsp_gen(WORD16 time); |
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163 |
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164 /*-------------------------------------------------------*/ |
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165 /* Prototypes of functions defined in this file. */ |
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166 /*-------------------------------------------------------*/ |
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167 // TPU Drivers... |
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168 |
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169 |
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170 // DSP Drivers... |
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171 void l1pddsp_synchro (UWORD8 switch_mode, UWORD8 camp_timeslot); |
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172 void l1pddsp_idle_prach_data (BOOL polling, UWORD8 cs_type, UWORD16 channel_request_data, |
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173 UWORD8 bsic, UWORD16 radio_freq); |
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174 void l1pddsp_idle_prach_power (UWORD8 txpwr, UWORD16 radio_freq, UWORD8 ts); |
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175 void l1pddsp_single_tx_block (UWORD8 burst_nb, UWORD8 *data, UWORD8 tsc, |
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176 UWORD16 radio_freq); |
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177 #if FF_L1_IT_DSP_USF |
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178 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq, |
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179 UWORD8 timeslot_no, BOOL ptcch_dl, BOOL usf_interrupt); |
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180 #else |
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181 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq, |
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182 UWORD8 timeslot_no, BOOL ptcch_dl); |
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183 #endif |
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184 void l1pddsp_transfer_mslot_ctrl (UWORD8 burst_nb, UWORD8 dl_bitmap, UWORD8 ul_bitmap, |
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185 UWORD8 *usf_table, UWORD8 mac_mode, UWORD8 *ul_buffer_index, |
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186 UWORD8 tsc, UWORD16 radio_freq, UWORD8 synchro_timeslot, |
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187 #if FF_L1_IT_DSP_USF |
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188 UWORD8 dsp_usf_interrupt |
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189 #else |
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190 UWORD8 usf_vote_enable |
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191 #endif |
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192 ); |
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193 void l1pddsp_transfer_mslot_power (UWORD8 *txpwr, UWORD16 radio_freq, UWORD8 ul_bitmap); |
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194 void l1pddsp_ul_ptcch_data (UWORD8 cs_type, UWORD16 channel_request_data, UWORD8 bsic, |
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195 UWORD16 radio_freq, UWORD8 timeslot_no); |
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196 void l1pddsp_interf_meas_ctrl (UWORD8 nb_meas_req); |
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197 void l1pddsp_transfer_meas_ctrl (UWORD8 meas_position); |
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198 |
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199 /*-------------------------------------------------------*/ |
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200 /* l1pd_afc() */ |
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201 /*-------------------------------------------------------*/ |
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202 /* Parameters : */ |
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203 /* Return : */ |
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204 /* Functionality : */ |
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205 /*-------------------------------------------------------*/ |
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206 void l1pd_afc(void) |
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207 { |
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208 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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209 l1ddsp_load_afc(l1s.afc); |
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210 #endif |
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211 #if (RF_FAM == 61) |
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212 l1dtpu_load_afc(l1s.afc); |
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213 #endif |
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214 } |
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215 |
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216 /*-------------------------------------------------------*/ |
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217 /* l1pdtpu_interf_meas() */ |
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218 /*-------------------------------------------------------*/ |
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219 /* Parameters : */ |
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220 /* Return : */ |
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221 /* Functionality : */ |
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222 /*-------------------------------------------------------*/ |
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223 UWORD8 l1pdtpu_interf_meas(UWORD16 radio_freq, |
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224 WORD8 agc, |
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225 UWORD8 lna_off, |
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226 UWORD8 meas_bitmap, |
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227 UWORD32 offset_serv, |
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228 UWORD16 win_id, |
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229 UWORD8 synchro_ts |
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230 #if (RF_FAM == 61) |
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231 ,UWORD8 if_ctl |
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232 #endif |
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233 ) |
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234 { |
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235 UWORD8 bit_mask = 0x80; |
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236 UWORD8 ts; |
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237 BOOL rf_programmed = FALSE; |
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238 UWORD8 count = 0; |
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239 |
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240 if(!win_id) |
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241 { |
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242 // Nothing programmed yet, we must avoid Mirror effect in Ctrl phase. |
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243 l1pdmacro_anchor(l1_config.params.rx_change_offset_time); |
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244 } |
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245 |
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246 for (ts=0; ts<8; ts++) |
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247 { |
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248 // the bitmap corresponds to that of the idle frame of the network!!! |
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249 #if ((CHIPSET==3)||(CHIPSET == 4)) |
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250 // limitation of 5 measurements for SAMSON (TPU RAM size limitation) |
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251 if((meas_bitmap & bit_mask)&&(count <= 4)) |
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252 #else |
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253 if(meas_bitmap & bit_mask) |
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254 #endif |
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255 { |
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256 UWORD16 local_win_id; |
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257 UWORD16 offset; |
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258 WORD16 when; |
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259 UWORD16 offset_chg; |
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260 |
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261 if((ts>synchro_ts) && (count==0)) |
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262 { |
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263 // The 1st Work does not contain any Interf meas. |
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264 // We must ovoid a possible Mirror effect for the rest of TS. |
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265 l1pdmacro_anchor(l1_config.params.rx_change_offset_time); |
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266 } |
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267 |
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268 // Increment nbr of meas. programmed. |
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269 count++; |
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270 |
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271 local_win_id = (8 - synchro_ts + ts) * BP_SPLIT; |
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272 if(local_win_id >= (BP_SPLIT * 8)) local_win_id -= BP_SPLIT * 8; // Modulo. |
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273 |
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274 // Compute offset |
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275 offset_chg = ((local_win_id * BP_DURATION) >> BP_SPLIT_PW2); |
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276 offset = offset_serv + offset_chg; |
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277 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE; |
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278 |
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279 if(!rf_programmed) |
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280 { |
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281 // Compute offset change timing |
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282 when = offset_chg + |
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283 PROVISION_TIME - |
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284 l1_config.params.rx_synth_setup_time - |
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285 EPSILON_OFFS; |
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286 |
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287 if(when < 0) when += TPU_CLOCK_RANGE; |
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288 |
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289 // Program TPU scenario |
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290 l1dmacro_offset (offset, when); // change TPU offset according to win_id |
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291 l1dmacro_rx_synth (radio_freq); // pgme SYNTH. |
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292 #if (RF_FAM !=61) |
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293 l1dmacro_agc (radio_freq, agc,lna_off); // pgme AGC. |
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294 #endif |
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295 |
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296 #if (RF_FAM == 61) |
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297 l1dmacro_agc (radio_freq, agc,lna_off, if_ctl); // pgme AGC. |
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298 #endif |
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299 |
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300 rf_programmed = TRUE; |
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301 } |
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302 else |
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303 { |
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304 // Compute offset change timing |
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305 when = offset_chg - BP_DURATION + PROVISION_TIME + PW_ACQUIS_DURATION + 20; |
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306 if(when < 0) when += TPU_CLOCK_RANGE; |
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307 |
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308 // Program TPU scenario |
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309 l1dmacro_offset (offset, when); // change TPU offset according to win_id |
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310 } |
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311 |
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312 #if (CODE_VERSION == SIMULATION) |
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313 l1dmacro_rx_ms (radio_freq, 1); // pgm PWR acquisition. |
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314 #else |
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315 #if (L1_MADC_ON == 1) |
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316 #if (RF_FAM == 61) |
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317 l1dmacro_rx_ms (radio_freq,INACTIVE); // pgm PWR acquisition. |
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318 #endif |
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319 #else |
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320 l1dmacro_rx_ms (radio_freq); // pgm PWR acquisition. |
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321 #endif |
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322 #endif |
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323 |
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324 l1dmacro_offset (offset_serv, IMM); // restore offset |
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325 } |
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326 |
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327 bit_mask >>= 1; |
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328 |
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329 } // for(ts... |
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330 |
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331 return(count); |
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332 } |
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333 |
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334 /*-------------------------------------------------------*/ |
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335 /* l1dtpu_serv_rx() */ |
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336 /*-------------------------------------------------------*/ |
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337 /* Parameters : */ |
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338 /* rx_id: range 0-7, first slot of RX group */ |
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339 /* rx_group_id: used in case |RX| |RX| */ |
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340 /* */ |
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341 /* Return : */ |
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342 /* Functionality : */ |
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343 /*-------------------------------------------------------*/ |
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344 void l1pdtpu_serv_rx_nb(UWORD16 radio_freq, UWORD8 agc, UWORD8 lna_off, |
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345 UWORD8 rx_id, UWORD32 offset_serv, UWORD8 num_rx, |
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346 UWORD8 rx_group_id, BOOL rx_done_flag,UWORD8 adc_active |
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347 #if (RF_FAM == 61) |
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348 ,UWORD8 csf_filter_choice |
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349 ,UWORD8 if_ctl |
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350 #endif |
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351 #if (NEW_SNR_THRESHOLD == 1) |
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352 ,UWORD8 saic_flag |
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353 #endif /* NEW_SNR_THRESHOLD*/ |
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354 ) |
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355 { |
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356 UWORD16 offset; |
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357 |
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358 #if (CODE_VERSION == SIMULATION) |
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359 UWORD32 tpu_w_page; |
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360 |
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361 if (hw.tpu_r_page==0) |
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362 tpu_w_page=1; |
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363 else |
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364 tpu_w_page=0; |
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365 |
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366 hw.rx_id[tpu_w_page][rx_group_id-1]=rx_id; |
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367 hw.num_rx[tpu_w_page][rx_group_id-1]=num_rx; |
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368 hw.rx_group_id[tpu_w_page]=rx_group_id; |
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369 #endif |
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370 |
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371 offset = offset_serv + (rx_id * BP_DURATION); |
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372 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE; |
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373 |
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374 if (rx_group_id == 1) |
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375 { |
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376 // Time tracking. |
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377 l1dmacro_synchro (l1_config.params.rx_change_synchro_time, offset_serv); // Adjust serving OFFSET. |
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378 |
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379 #if L2_L3_SIMUL |
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380 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) |
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381 buffer_trace(3, 0x43, offset_serv, l1s.actual_time.fn, 0); |
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382 #endif |
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383 #endif |
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384 |
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385 // Change offset to align on RX. |
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386 l1dmacro_offset(offset, IMM); |
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387 |
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388 // Program Synth. |
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389 // Program ADC measurement |
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390 // Program AGC. |
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391 l1dmacro_rx_synth(radio_freq); |
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392 if(adc_active == ACTIVE) |
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393 l1dmacro_adc_read_rx(); |
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394 |
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395 l1dmacro_agc (radio_freq, agc, lna_off |
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396 #if (RF_FAM == 61) |
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397 ,if_ctl |
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398 #endif |
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399 ); |
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400 } |
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401 else |
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402 { |
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403 // Change offset to align on RX. |
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404 l1dmacro_offset(offset, IMM); // Change offset to align on RX. |
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405 } |
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406 |
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407 l1pdmacro_rx_up (radio_freq |
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408 #if (RF_FAM == 61) |
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409 ,adc_active |
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410 ,csf_filter_choice |
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411 #endif |
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412 #if (NEW_SNR_THRESHOLD == 1) |
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413 ,saic_flag |
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414 #endif /* NEW_SNR_THRESHOLD*/ |
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415 |
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416 ); // RX window opened. |
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417 l1pdmacro_rx_down(radio_freq, num_rx, rx_done_flag); // RX window closed. |
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418 |
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419 // Restore offset to synchro value. |
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420 l1dmacro_offset (offset_serv, IMM); |
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421 } |
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|
422 |
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423 /*-------------------------------------------------------*/ |
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424 /* l1dtpu_serv_tx() */ |
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425 /*-------------------------------------------------------*/ |
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426 /* Parameters : */ |
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427 /* Return : */ |
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428 /* Functionality : */ |
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429 /*-------------------------------------------------------*/ |
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430 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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431 #ifndef ABB_RAMP_UP_TIME //Flexi ABB Delays defines it in tpudrvXX.h |
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432 #define ABB_RAMP_UP_TIME 32 // maximum time for ramp up |
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433 #endif |
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434 |
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|
435 #ifndef ABB_RAMP_DELAY//Flexi ABB Delays defines it in tpudrvXX.h |
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436 #define ABB_RAMP_DELAY 6 // minimum ramp delay APCDEL |
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|
437 #endif |
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|
438 |
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|
439 #ifndef ABB_BULON_HOLD_TIME //Flexi ABB Delays defines it in tpudrvXX.h |
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440 #define ABB_BULON_HOLD_TIME 32 // min. hold time for BULON after BULENA down |
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441 #endif |
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|
442 |
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|
443 |
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|
444 #endif |
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445 void l1pdtpu_serv_tx(UWORD16 radio_freq, |
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446 UWORD8 timing_advance, |
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447 UWORD32 offset_serv, |
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448 UWORD8 tx_id, |
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449 UWORD8 num_tx, |
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450 UWORD8 tx_group_id, |
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451 UWORD8 switch_flag, |
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452 BOOL burst_type, |
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453 BOOL rx_flag, |
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454 UWORD8 adc_active) |
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|
455 { |
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|
456 WORD16 time; |
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457 UWORD32 offset_tx; |
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458 UWORD32 timing_advance_in_qbit = (UWORD32)timing_advance << 2; |
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459 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) |
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460 UWORD16 apcdel1_data, apcdel1_data_up; |
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|
461 #endif |
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|
462 UWORD8 i; |
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463 static UWORD8 static_switch_flag = 0; |
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|
464 |
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465 #if (CODE_VERSION == SIMULATION) |
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466 UWORD32 tpu_w_page; |
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|
467 |
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|
468 if (hw.tpu_r_page==0) |
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|
469 tpu_w_page=1; |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
470 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
471 tpu_w_page=0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
472 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
473 hw.tx_id[tpu_w_page][tx_group_id-1]=tx_id; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
474 hw.num_tx[tpu_w_page][tx_group_id-1]=num_tx; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
475 hw.tx_group_id[tpu_w_page]=tx_group_id; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
476 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
477 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
478 // Reset timing advance if TA_ALGO not enabled. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
479 #if !TA_ALGO |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
480 timing_advance_in_qbit = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
481 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
482 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
483 // In case another group of TX bursts is called, the previous slot was a hole |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 // An IT has to be generated to the DSP so that ramps and power level are reloaded |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485 // This does not apply to combinations of PRACH and TX NB |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
486 if ((tx_group_id > 1) && (!static_switch_flag)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
488 // exact timing for generation of IT during hole not required but |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
489 // time > time of previous ramp down (BULENA -> BULON down = 32 qb) + margin (10 qb) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
490 #if (RF_FAM != 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
491 time = TX_TABLE[tx_id-1] + PROVISION_TIME + ABB_BULON_HOLD_TIME + 10 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 - l1_config.params.prg_tx_gsm; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
494 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 #if (RF_FAM == 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
496 time = TX_TABLE[tx_id-1] + PROVISION_TIME + APC_RAMP_DOWN_TIME + 10 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
497 - l1_config.params.prg_tx_gsm; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
498 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
499 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
500 if (burst_type == TX_NB_BURST) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
501 time -= timing_advance_in_qbit; // time can never be negative here |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
502 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 l1pdmacro_it_dsp_gen(time); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
506 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 if (tx_group_id == 1) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 //MS TX, set ABB in MS mode |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
512 // ABB set to MS mode if |TX|TX|.., |TX|PRACH|, |PRACH|TX| or |PRACH|PRACH| |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
513 // switch_flag is set for the first burst of TX/PRACH or PRACH/PRACH combinations |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
514 // MS mode in ABB must be maintained for second burst (static_switch_flag) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
515 if ((num_tx > 1) || (switch_flag) || (static_switch_flag)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
516 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl | B_MSLOT; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
517 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
518 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
519 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
520 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
521 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
522 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
523 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524 // handle special case |TX| |TX|TX| |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 //MS TX, set ABB in MS mode |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 if ((num_tx > 1) || (switch_flag) || (static_switch_flag)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl | B_MSLOT; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
533 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 // Compute offset value for TX. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX ! |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 if ((burst_type == TX_NB_BURST) || (switch_flag==1)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
537 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
538 offset_tx = offset_serv + TX_TABLE[tx_id] + PROVISION_TIME |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
539 - l1_config.params.prg_tx_gsm - timing_advance_in_qbit; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
540 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
541 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
542 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
543 offset_tx = offset_serv + TX_TABLE[tx_id] + PROVISION_TIME |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
544 - l1_config.params.prg_tx_gsm; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
545 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
546 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
547 // offset_tx mod 5000 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
548 if (offset_tx >= TPU_CLOCK_RANGE) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
549 offset_tx -= TPU_CLOCK_RANGE; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
551 if(rx_flag == TRUE) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
552 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
553 time = offset_tx - |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
554 l1_config.params.tx_synth_setup_time - |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
555 EPSILON_OFFS |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
556 - offset_serv; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
557 if ((burst_type == TX_NB_BURST) || (switch_flag==1)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
558 time += timing_advance_in_qbit - TA_MAX; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
559 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
560 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
561 time = TPU_CLOCK_RANGE - EPSILON_SYNC; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
562 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
563 if (time < 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
564 time += TPU_CLOCK_RANGE; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
565 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
566 if (!static_switch_flag) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
567 l1dmacro_offset (offset_tx, (WORD32) time); // load OFFSET for TX before each burst. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
568 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
569 #if L2_L3_SIMUL |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
570 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
571 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
572 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
573 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
574 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
575 time=0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
576 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
577 // program PLL only if no TX control carried out in same frame: |TX| |TX|TX| possible |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
578 // |PRACH|TX|, |TX|PRACH| or |PRACH|PRACH| also possible |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
579 if (tx_group_id == 1) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
580 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
581 l1pdmacro_tx_synth(radio_freq); // load SYNTH. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
582 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
583 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
584 if (!static_switch_flag) // window opened for previous time slot (TX/PRACH or PRACH/PRACH) |
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585 l1pdmacro_tx_up(radio_freq); // TX window opened |
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|
586 |
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|
587 |
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588 #if (CODE_VERSION == SIMULATION) |
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|
589 if (burst_type == TX_RA_BURST) |
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|
590 { |
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|
591 time += l1_config.params.tx_ra_duration; |
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|
592 } |
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|
593 else |
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|
594 { |
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|
595 if (num_tx > 1) |
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|
596 // num_tx * BP_DURATION |
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|
597 time += TX_TABLE[num_tx - 1] + l1_config.params.tx_nb_duration; |
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|
598 else |
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|
599 time += l1_config.params.tx_nb_duration; |
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|
600 } |
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|
601 #else |
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diff
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|
602 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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parents:
diff
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|
603 // Read APCDEL1 register DELU(4:0): delay of ramp up start, DELD (9:5) delay of ramp down start |
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diff
changeset
|
604 // This value is used for computations in MS TX or TX/PRACH combinations |
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parents:
diff
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|
605 // This value is not modified by the computations |
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diff
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|
606 apcdel1_data = (l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 >> 6) & 0x03ff; |
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|
607 apcdel1_data_up = apcdel1_data & 0x001f; //delay of ramp up start |
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parents:
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|
608 #endif |
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parents:
diff
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|
609 |
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|
610 #if (RF_FAM == 61) |
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parents:
diff
changeset
|
611 // Read APCDEL1 register DELU(4:0): delay of ramp up start, DELD (9:5) delay of ramp down start |
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parents:
diff
changeset
|
612 // This value is used for computations in MS TX or TX/PRACH combinations |
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parents:
diff
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|
613 // This value is not modified by the computations |
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parents:
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|
614 apcdel1_data = (l1s_dsp_com.dsp_ndb_ptr->d_apcdel1) & 0x03ff; |
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parents:
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|
615 apcdel1_data_up = apcdel1_data & 0x001f; //delay of ramp up start |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
616 #endif |
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parents:
diff
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|
617 |
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Mychaela Falconia <falcon@freecalypso.org>
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|
618 if (!switch_flag) |
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diff
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|
619 { |
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|
620 if (burst_type == TX_NB_BURST) |
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parents:
diff
changeset
|
621 { |
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parents:
diff
changeset
|
622 // If PRACH precedes TX normal burst(s) we have to add BP_DURATION |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
623 if (static_switch_flag) |
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|
624 time += BP_DURATION; |
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parents:
diff
changeset
|
625 |
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diff
changeset
|
626 // generate DSP IT for each TX slot after ramp up |
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parents:
diff
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|
627 // Margin: |
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parents:
diff
changeset
|
628 // ABB_RAMP_DELAY = 4*1.5bits internal ABB delay BULENA ON -> ramp up |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
629 // apcdel1_data_up = additional delay BULENA ON -> ramp up |
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parents:
diff
changeset
|
630 // ABB_RAMP_UP_TIME: maximum time for ramp up: 16 coeff. |
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parents:
diff
changeset
|
631 // 10 qbits of additional margin |
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parents:
diff
changeset
|
632 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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parents:
diff
changeset
|
633 for (i=0; i<num_tx; i++) |
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parents:
diff
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|
634 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + i*BP_DURATION + apcdel1_data_up + 10); |
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parents:
diff
changeset
|
635 #endif |
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parents:
diff
changeset
|
636 |
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parents:
diff
changeset
|
637 #if (RF_FAM == 61) |
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parents:
diff
changeset
|
638 for (i=0; i<num_tx; i++) |
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parents:
diff
changeset
|
639 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + i*BP_DURATION + apcdel1_data_up + 10); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
640 #endif |
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parents:
diff
changeset
|
641 |
b6a5e36de839
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parents:
diff
changeset
|
642 |
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parents:
diff
changeset
|
643 if (num_tx > 1) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
644 // (num_tx - 1) * BP_DURATION + normal burst duration |
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parents:
diff
changeset
|
645 time += TX_TABLE[num_tx - 1] + l1_config.params.tx_nb_duration - (num_tx - 1); |
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parents:
diff
changeset
|
646 else |
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parents:
diff
changeset
|
647 time += l1_config.params.tx_nb_duration; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
648 } |
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parents:
diff
changeset
|
649 else //PRACH |
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parents:
diff
changeset
|
650 { |
b6a5e36de839
src/cs: initial import from Magnetite
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parents:
diff
changeset
|
651 // If TX NB precedes PRACH we have to add BP_DURATION and TA (in qbits) |
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parents:
diff
changeset
|
652 if (static_switch_flag == 1) |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
653 { |
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parents:
diff
changeset
|
654 if (timing_advance_in_qbit > 240) // clip TA, cf. comment below |
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parents:
diff
changeset
|
655 timing_advance_in_qbit = 240; |
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parents:
diff
changeset
|
656 time += BP_DURATION + timing_advance_in_qbit; |
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diff
changeset
|
657 } |
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parents:
diff
changeset
|
658 // If PRACH precedes PRACH we have to add BP_DURATION |
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changeset
|
659 else if (static_switch_flag == 2) |
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parents:
diff
changeset
|
660 time += BP_DURATION ; |
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parents:
diff
changeset
|
661 |
b6a5e36de839
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diff
changeset
|
662 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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changeset
|
663 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); |
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parents:
diff
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|
664 #endif |
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changeset
|
665 |
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diff
changeset
|
666 #if (RF_FAM == 61) |
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parents:
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changeset
|
667 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); |
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parents:
diff
changeset
|
668 #endif |
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parents:
diff
changeset
|
669 |
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changeset
|
670 time += l1_config.params.tx_ra_duration; |
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diff
changeset
|
671 } |
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parents:
diff
changeset
|
672 |
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parents:
diff
changeset
|
673 } |
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diff
changeset
|
674 else if (switch_flag == 1) // |TX|PRACH| or |PRACH|TX| |
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parents:
diff
changeset
|
675 { |
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changeset
|
676 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
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parents:
diff
changeset
|
677 // => ABB windows are opened as for TX_NB in MS mode |
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parents:
diff
changeset
|
678 // => Ramp up start of PRACH is delayed inside this window by the TA of the TX_NB |
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parents:
diff
changeset
|
679 // => DSP inserts dummy bits such that ramp and modulation match |
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parents:
diff
changeset
|
680 // Rem.: the TA passed for the PRACH is the one for the following TX_NB!!! |
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diff
changeset
|
681 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) || (RF_FAM == 61) |
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parents:
diff
changeset
|
682 // In combinations of TX_NB and PRACH apcdel1_bis and apcdel2_bis apply to the PRACH |
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parents:
diff
changeset
|
683 UWORD16 apcdel1_bis_data, apcdel1_bis_data_up, apcdel2_bis_data_up, prach_delay; |
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parents:
diff
changeset
|
684 API d_ctrl_abb_gprs; |
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parents:
diff
changeset
|
685 |
b6a5e36de839
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parents:
diff
changeset
|
686 // clip TA (in qbit): max. TA supported = BP_DURATION - PRACH duration - max. ramp time |
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parents:
diff
changeset
|
687 // = 625 - 88*4 - 32 = 241 |
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parents:
diff
changeset
|
688 if (timing_advance_in_qbit > 240) |
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parents:
diff
changeset
|
689 timing_advance_in_qbit = 240; |
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parents:
diff
changeset
|
690 |
b6a5e36de839
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parents:
diff
changeset
|
691 prach_delay = apcdel1_data_up + timing_advance_in_qbit; |
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diff
changeset
|
692 apcdel1_bis_data_up = prach_delay & 0x001f; |
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parents:
diff
changeset
|
693 apcdel2_bis_data_up = (prach_delay >> 5) & 0x001f; |
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parents:
diff
changeset
|
694 |
b6a5e36de839
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parents:
diff
changeset
|
695 // For ramp down delay we need to keep the original value from APCDEL1 (bits 9:5) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
696 // APCDEL2 default value is '0' |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
697 apcdel1_bis_data = apcdel1_bis_data_up | (apcdel1_data & 0x03e0); |
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parents:
diff
changeset
|
698 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
699 #if(RF_FAM != 61) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
700 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1_bis = (apcdel1_bis_data << 6) | 0x04; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
701 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2_bis = (apcdel2_bis_data_up << 6) | 0x34; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
702 #else |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
703 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1_bis = (apcdel1_bis_data ); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
704 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2_bis = (apcdel2_bis_data_up); |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
705 #endif |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
706 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
707 if (burst_type == TX_RA_BURST) // |PRACH|TX| |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
708 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
709 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
710 #if(RF_FAM != 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
711 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + prach_delay + 10); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
712 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
713 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + prach_delay + 10); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
714 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
715 // apcdel1_bis, apcdel2_bis must be programmed for the current ts (PRACH) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
716 // here we need to overwrite (mask) bits for APCDEL1, APCDEL2 programming done in l1pddsp_transfer_mslot_power() |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
717 d_ctrl_abb_gprs = l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id]; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
718 d_ctrl_abb_gprs |= ((1 << B_BULRAMPDEL_BIS) | (1 << B_BULRAMPDEL2_BIS)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
719 d_ctrl_abb_gprs &= ~((1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
720 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id] = d_ctrl_abb_gprs; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
721 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
722 else // |TX|PRACH| |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
723 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
724 #if(RF_FAM != 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
725 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
726 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
727 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
728 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
729 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
730 // apcdel1_bis, apcdel2_bis must be programmed for the next ts (PRACH) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
731 d_ctrl_abb_gprs = l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id + 1]; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
732 d_ctrl_abb_gprs |= ((1 << B_BULRAMPDEL_BIS) | (1 << B_BULRAMPDEL2_BIS)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
733 d_ctrl_abb_gprs &= ~((1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
734 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id + 1] = d_ctrl_abb_gprs; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
735 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
736 #endif // ANALOG |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
737 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
738 static_switch_flag = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
739 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
740 #endif // DSP == 33 || DSP == 34 || (DSP == 36) || (DSP == 37) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
741 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
742 else if (switch_flag == 2) // |PRACH|PRACH| |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
743 // Combination handled by programming ABB with MS mode = 1 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
744 // => first burst length of first PRACH = BP_DURATION |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
745 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
746 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
747 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
748 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
749 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
750 #if (RF_FAM == 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
751 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
752 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
753 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
754 static_switch_flag = 2; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
755 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
756 #endif //Codeversion |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
757 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
758 // In case of combinations TX_NB/PRACH or PRACH/PRACH the TX window is kept open |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
759 if (!switch_flag) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
760 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
761 l1pdmacro_tx_down(radio_freq, time, switch_flag, timing_advance_in_qbit,adc_active); // TX window closed |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
762 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
763 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
764 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
765 static_switch_flag = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
766 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
767 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
768 #if L2_L3_SIMUL |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
769 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
770 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
771 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
772 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
773 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
774 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
775 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
776 /* l1pddsp_synchro() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
777 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
778 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
779 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
780 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
781 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
782 void l1pddsp_synchro(UWORD8 switch_mode, UWORD8 camp_timeslot) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
783 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
784 // Set "b_abort" to TRUE. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
785 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= (1 << B_TASK_ABORT); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
786 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
787 // Set switch mode within "b_switch_to_gprs" & "b_switch_to_gms" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
788 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = (switch_mode << B_SWITCH); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
789 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
790 // In case of a switch to GPRS_SCHEDULER, last_used_txpwr is set to "NO_TXPWR" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
791 // in order to force GSM ramp programming when the MS will switch back to |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
792 // GSM_SCHEDULER |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
793 // Moreover, the d_win_start_gprs register must be initialized only during the |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
794 // GSM->GPRS switch too. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
795 if(switch_mode == GPRS_SCHEDULER) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
796 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
797 l1s.last_used_txpwr = NO_TXPWR; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
798 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
799 // Set camp timeslot. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
800 l1ps_dsp_com.pdsp_ndb_ptr->d_win_start_gprs = camp_timeslot; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
801 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
802 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
803 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
804 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
805 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
806 /* l1pddsp_idle_prach_data() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
807 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
808 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
809 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
810 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
811 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
812 void l1pddsp_idle_prach_data(BOOL polling, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 UWORD8 cs_type, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
814 UWORD16 channel_request_data, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
815 UWORD8 bsic, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
816 UWORD16 radio_freq) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
817 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
818 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
819 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 // UL on TS=3. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
821 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> 3; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
822 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
823 // Swap I/Q management. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
824 swap_bit = l1ps_swap_iq_ul(radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
825 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
826 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 // Load UL buffer according to "polling" bit. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
828 if(polling) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
829 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 // Select first UL polling buffer. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
831 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 8; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
833 // Store CS type. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = cs_type; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
835 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
836 // Store UL data block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 if(cs_type == CS_PAB8_TYPE) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
839 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2] = ((API)(bsic << 2)) | |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 ((API)(channel_request_data) << 8); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][3] = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
843 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2] = ((API)(channel_request_data) << 5); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][3] = ((API)(bsic << 10)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
847 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 // Set "b_access_prach" to indicate 1 Prach only to DSP. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= (1 << B_ACCESS_PRACH); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 // Select first UL data buffer. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
856 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 // Store CS type. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][0] = cs_type; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
860 // Store UL data block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 if(cs_type == CS_PAB8_TYPE) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][1] = ((API)(bsic << 2)) | |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 ((API)(channel_request_data) << 8); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][2] = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
868 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][1] = ((API)(channel_request_data) << 5); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][2] = ((API)(bsic << 10)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
873 if (l1pa_l1ps_com.pra_info.prach_alloc == FIX_PRACH_ALLOC) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 // Set fix alloc bit. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs |= (2 << B_MAC_MODE); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
879 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 // Reset MAC mode to dynamic allocation |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
881 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= ~(3 << B_MAC_MODE); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
882 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
883 #if !FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
884 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
885 // Enable USF vote on timeslot 0 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
886 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = 0x80; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
887 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
888 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
889 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
890 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
891 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
892 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
893 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
894 /* l1pddsp_idle_prach_power() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
895 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
896 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
897 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
898 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
899 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
900 void l1pddsp_idle_prach_power(UWORD8 txpwr, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
901 UWORD16 radio_freq, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
902 UWORD8 ts) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
903 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
904 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
905 UWORD16 pwr_data; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
906 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
907 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
908 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) ) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
909 // Force FIXED transmit power if requested. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
910 if(l1_config.tx_pwr_code == 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
912 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = l1_config.params.fixed_txpwr; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
913 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
914 // Control bitmap: update RAMP, use RAMP[5][..]. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
915 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
916 ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
917 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 // Store Ramp. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
919 #if (CODE_VERSION != SIMULATION) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
920 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[5], |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
921 0, /* not used */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
922 0, /* not used */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
923 1 /* arbitrary value for arfcn */ ); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
924 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
926 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
927 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
928 // Get H/W value corresponding to txpwr command. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
929 pwr_data = Cust_get_pwr_data(txpwr, radio_freq |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930 #if(REL99 && FF_PRF) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 ,1 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
933 ); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
934 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
935 // Store Transmit power. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = ((pwr_data << 6) | 0x12); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 // Control bitmap: update RAMP, use RAMP[5][..]. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941 // Store Ramp. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 #if (CODE_VERSION != SIMULATION) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[5][0]), txpwr, txpwr, radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 #if (RF_FAM == 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 // Force FIXED transmit power if requested. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 if(l1_config.tx_pwr_code == 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = l1_config.params.fixed_txpwr; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 // Control bitmap: update RAMP, use RAMP[5][..]. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 // Store Ramp. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 #if (DSP ==38) || (DSP == 39) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[5], |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 0, /* not used */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 0, /* not used */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 1 /* arbitrary value for arfcn */ ); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 // Get H/W value corresponding to txpwr command. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 pwr_data = Cust_get_pwr_data(txpwr, radio_freq |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 #if(REL99 && FF_PRF) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 ,1 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 ); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 // Store Transmit power. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = (API) (pwr_data); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 // Control bitmap: update RAMP, use RAMP[5][..]. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 // Store Ramp. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 #if(DSP == 38) || (DSP == 39) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[5][0]), txpwr, txpwr, radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 #endif //RF_FAM == 61 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 /* l1pddsp_single_block() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
992 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
993 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
994 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
995 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
996 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
997 void l1pddsp_single_tx_block(UWORD8 burst_nb, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
998 UWORD8 *data, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
999 UWORD8 tsc, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1000 UWORD16 radio_freq) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1001 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1002 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1003 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1004 // Burst number within a block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1005 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1006 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1007 // UL on TS=3. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1008 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> 3; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1009 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1010 // Swap I/Q management. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1011 swap_bit = l1ps_swap_iq_ul(radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1012 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1013 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1014 // Select first UL polling buffer. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1015 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 8; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1016 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1017 // Store CS type: CS1 for Polling. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1018 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS1_TYPE_POLL; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1019 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1020 if(burst_nb == BURST_1) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1021 // Store UL data block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1022 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1023 API *ul_block_ptr = &(l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2]); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1024 UWORD8 i,j; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1025 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1026 // Copy first 22 bytes in the first 11 words after header. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1027 for (i=0, j=0; j<11; j++) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1028 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1029 ul_block_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1030 i += 2; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1031 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1032 // Copy last UWORD8 (23rd) in the 12th word after header. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1033 ul_block_ptr[11] = data[22]; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1034 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1035 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1036 // Training sequence. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1037 // Rem: bcch_freq_ind is set within Hopping algo. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1038 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1039 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1040 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1041 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1042 /* l1pddsp_idle_rx_nb() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1043 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1044 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1045 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1046 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1047 /*-------------------------------------------------------*/ |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1048 #if FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1049 void l1pddsp_idle_rx_nb(UWORD8 burst_nb, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1050 UWORD8 tsc, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1051 UWORD16 radio_freq, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1052 UWORD8 timeslot_no, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1053 BOOL ptcch_dl, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1054 BOOL usf_interrupt) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1055 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1056 void l1pddsp_idle_rx_nb(UWORD8 burst_nb, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1057 UWORD8 tsc, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1058 UWORD16 radio_freq, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1059 UWORD8 timeslot_no, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1060 BOOL ptcch_dl) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1061 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1062 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1063 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1064 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1065 // DL on TS=0. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1066 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= 0x80 >> timeslot_no; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1067 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1068 // Swap I/Q management. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1069 swap_bit = l1ps_swap_iq_dl(radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1070 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= swap_bit << 15; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1071 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1072 if(ptcch_dl) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1073 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1074 // PTCCH/DL case must be flagged to DSP. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1075 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= (1 << B_PTCCH_DL); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1076 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1077 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1078 // Burst number within a block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1079 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1080 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1081 // Channel coding is forced to CS1. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1082 l1ps_dsp_com.pdsp_ndb_ptr->a_ctrl_ched_gprs[timeslot_no] = CS1_TYPE_DATA; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1083 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1084 // pass information to DSP which good USF value is to be expected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1085 l1ps_dsp_com.pdsp_ndb_ptr->a_usf_gprs[0] = (API) 0x07; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1086 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1087 #if FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1088 // In case of connection establishment mode with dynamic or fixed |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1089 // allocation scheme we need to request the DSP USF interrupt for PRACH |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1090 // scheduling. Latched by DSP during Work3 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1091 if (burst_nb == 3) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1092 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1093 if (usf_interrupt) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1094 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable |= (1 << B_USF_IT); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1095 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1096 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable &= ~(1 << B_USF_IT); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1097 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1098 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1099 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1100 // RIF receiver algorithm: select 156.25. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1101 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= 0xFFFF ^ (1 << B_RIF_RX_MODE); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1102 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1103 // Training sequence. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1104 // Rem: bcch_freq_ind is set within Hopping algo. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1105 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1106 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1107 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1108 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1109 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1110 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1111 /* l1pddsp_transfer_mslot_ctrl() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1112 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1113 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1114 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1115 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1116 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1117 void l1pddsp_transfer_mslot_ctrl(UWORD8 burst_nb, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1118 UWORD8 dl_bitmap, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1119 UWORD8 ul_bitmap, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1120 UWORD8 *usf_table, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1121 UWORD8 mac_mode, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1122 UWORD8 *ul_buffer_index, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1123 UWORD8 tsc, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1124 UWORD16 radio_freq, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1125 UWORD8 synchro_timeslot, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1126 #if FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1127 UWORD8 dsp_usf_interrupt |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1128 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1129 UWORD8 usf_vote_enable |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1130 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1131 ) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1132 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1133 UWORD8 i; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1134 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1135 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1136 // Burst number within a block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1137 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1138 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1139 // DL bitmap. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1140 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs = dl_bitmap; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1141 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1142 // UL bitmap. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1143 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs = ul_bitmap; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1144 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1145 // Swap I/Q management for DL. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1146 swap_bit = l1ps_swap_iq_dl(radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1147 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= swap_bit << 15; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1148 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1149 // Swap I/Q management for UL. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1150 swap_bit = l1ps_swap_iq_ul(radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1151 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1152 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1153 if(burst_nb == 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1154 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1155 // Store USF table |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1156 for(i=0;i<(8 - synchro_timeslot);i++) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1157 l1ps_dsp_com.pdsp_ndb_ptr->a_usf_gprs[i] = usf_table[i+synchro_timeslot]; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1158 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1159 // Automatic CS detection. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1160 for(i=0;i<8;i++) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1161 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1162 l1ps_dsp_com.pdsp_ndb_ptr->a_ctrl_ched_gprs[i] = CS_AUTO_DETECT; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1163 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1164 // Select first UL polling buffer. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1165 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[i] = ul_buffer_index[i]; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1166 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1167 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1168 #if !FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1169 // USF vote enable programming |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1170 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1171 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1172 // Multislot TX allowed and usf_vote_enable suported: programs usf_vote_enable |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1173 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = usf_vote_enable; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1174 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1175 // Single slot TX only and usf_vote_enable not supported |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1176 // Modify MAC mode |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1177 if (usf_vote_enable) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1178 // USF vote enabled --> Set MAC mode to dynamic mode |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1179 mac_mode = DYN_ALLOC; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1180 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1181 // USF vote disabled --> Set MAC mode to fixed mode |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1182 mac_mode = FIX_ALLOC_NO_HALF; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1183 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1184 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1185 #endif // !FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1186 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1187 // MAC mode. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1188 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= ~(3 << B_MAC_MODE); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1189 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs |= mac_mode << B_MAC_MODE; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1190 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1191 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1192 #if FF_L1_IT_DSP_USF |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1193 if(burst_nb == 3) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1194 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1195 // Program DSP to generate an interrupt once USF available if |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1196 // required. Latched by DSP during Work3. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1197 if (dsp_usf_interrupt) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1198 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = (1 << B_USF_IT); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1199 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1200 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1201 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1202 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1203 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1204 // RIF receiver algorithm: select 156.25. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1205 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= 0xFFFF ^ (1 << B_RIF_RX_MODE); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1206 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1207 // d_fn |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1208 // ---- |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1209 // bit [0..7] -> b_fn_report, unused for GPRS |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1210 // bit [8..15] -> b_fn_sid , FN%104 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1211 l1s_dsp_com.dsp_db_w_ptr->d_fn = ((l1s.next_time.fn_mod104)<<8); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1212 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1213 // Training sequence. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1214 // Rem: bcch_freq_ind is set within Hopping algo. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1215 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1216 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1217 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1218 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1219 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1220 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1221 /* l1pddsp_transfer_mslot_power() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1222 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1223 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1224 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1225 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1226 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1227 void l1pddsp_transfer_mslot_power(UWORD8 *txpwr, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1228 UWORD16 radio_freq, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1229 UWORD8 ul_bitmap) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1230 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1231 #define NO_TX 100 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1232 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1233 UWORD16 i; // 16 bit needed for shifting pupose. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1234 UWORD8 last_TX = NO_TX; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1235 UWORD8 txpwr_ramp_up; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1236 UWORD8 txpwr_ramp_down; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1237 UWORD8 cpt_TX = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1238 UWORD8 ts_mask; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1239 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1240 #if (REL99 && FF_PRF) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1241 UWORD8 number_uplink_timeslot = 0 ; // number of uplink timeslot for power reduction feature |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1242 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1243 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1244 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1245 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1246 UWORD16 pwr_data; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1247 UWORD16 d_ramp_idx; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1248 WORD16 ts_conv; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1249 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1250 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1251 //Locosto #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1252 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1253 // This function is called with an ul_bitmap which represents the abolute |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1254 // position of any Tx bursts in this frame. This bitmap has already |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1255 // absorbed any synchro change (in dl_tn), hence we need to do some |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1256 // processing to recover the actual Tx timeslot number which is used |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1257 // as an index into the txpwr array. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1258 // |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1259 // Example : MS Class 8 with 4 Rx and 1 Tx : |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1260 // |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1261 // |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1262 // dl_ts_alloc : 0x0f 0 0 0 0 R R R R |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1263 // ul_ts_alloc : 0x02 0 0 0 0 0 0 T 0 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1264 // shift + combine : 0 0 0 0 R R R R 0 T |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1265 // set dl_tn=4 : R R R R 0 T 0 0 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1266 // ul_bitmap : 0x04 0 0 0 0 0 1 0 0 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1267 // i : 5 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1268 // |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1269 // Example : MS Class 8 with 1 Rx and 1 Tx on TS=7 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1270 // |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1271 // dl_ts_alloc : 0x01 0 0 0 0 0 0 0 R |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1272 // ul_ts_alloc : 0x01 0 0 0 0 0 0 0 T |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1273 // shift + combine : 0 0 0 0 0 0 0 R 0 0 T |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1274 // set dl_tn=7 : R 0 0 T 0 0 0 0 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1275 // ul_bitmap : 0x10 0 0 0 1 0 0 0 0 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1276 // i : 3 |
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parents:
diff
changeset
|
1277 // |
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parents:
diff
changeset
|
1278 // We recover the actual timeslot from the ul_bitmap by the following |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1279 // method : |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1280 // |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1281 // ts = (i + dl_tn) - 3 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1282 // |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1283 // Where i is the loopindex usd to detect "1" in the ul_bitmap. |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1284 // This works for MS class 8 because (3 <= i <= 5) if the |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1285 // multislot class is respected. |
b6a5e36de839
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parents:
diff
changeset
|
1286 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1287 #if (REL99 && FF_PRF)// power reduction feature |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1288 for (i=0; i<8; i++) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1289 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1290 // computed number of uplink timeslot in order to determine uplink power reduction |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1291 ts_mask = (0x80>>i); |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1292 if (ul_bitmap & ts_mask) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1293 number_uplink_timeslot++; |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1294 } |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1295 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1296 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1297 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1298 ts_conv = l1a_l1s_com.dl_tn - 3; |
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parents:
diff
changeset
|
1299 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1300 // Index of the programmed ramps |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1301 d_ramp_idx = 0; |
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parents:
diff
changeset
|
1302 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1303 for(i=0;i<8;i++) |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1304 { |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1305 // Program Transmit power and ramp for allocated timeslots. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1306 if(ul_bitmap & (0x80>>i)) |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1307 { |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1308 // Fixe transmit power. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1309 if(l1_config.tx_pwr_code == 0) |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1310 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1311 // Store Transmit power. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1312 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = l1_config.params.fixed_txpwr; |
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parents:
diff
changeset
|
1313 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1314 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..]. |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1315 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1316 ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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parents:
diff
changeset
|
1317 |
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parents:
diff
changeset
|
1318 // Store Ramp. |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1319 #if (RF_FAM == 61) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1320 #if (DSP ==38) || (DSP == 39) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1321 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx++], |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1322 0, /* not used */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1323 0, /* not used */ |
b6a5e36de839
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parents:
diff
changeset
|
1324 1 /* arbitrary value for arfcn */ ); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1325 #endif |
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parents:
diff
changeset
|
1326 #else |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1327 #if (CODE_VERSION != SIMULATION) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1328 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx++], |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1329 0, /* not used */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1330 0, /* not used */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1331 1 /* arbitrary value for arfcn */ ); |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1332 #endif |
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parents:
diff
changeset
|
1333 #endif |
b6a5e36de839
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parents:
diff
changeset
|
1334 } |
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parents:
diff
changeset
|
1335 else |
b6a5e36de839
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parents:
diff
changeset
|
1336 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1337 // count the number of TX windows |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1338 cpt_TX ++; |
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parents:
diff
changeset
|
1339 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1340 // Get power amplifier data. |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1341 #if(REL99 && FF_PRF) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1342 pwr_data = Cust_get_pwr_data(txpwr[i+ts_conv], radio_freq, number_uplink_timeslot); |
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parents:
diff
changeset
|
1343 #else |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1344 pwr_data = Cust_get_pwr_data(txpwr[i+ts_conv], radio_freq); |
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parents:
diff
changeset
|
1345 #endif |
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parents:
diff
changeset
|
1346 |
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parents:
diff
changeset
|
1347 |
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parents:
diff
changeset
|
1348 // Store Transmit power. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1349 #if(RF_FAM == 61) |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1350 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = (pwr_data); |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1351 #else |
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parents:
diff
changeset
|
1352 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = ((pwr_data << 6) | 0x12); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1353 #endif |
b6a5e36de839
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parents:
diff
changeset
|
1354 |
b6a5e36de839
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parents:
diff
changeset
|
1355 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..] for slot i. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1356 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
b6a5e36de839
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parents:
diff
changeset
|
1357 |
b6a5e36de839
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parents:
diff
changeset
|
1358 // Store Ramp. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1359 // ========== |
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parents:
diff
changeset
|
1360 // for the 1st TX the RAMP is: RAMP_UP_TX1 / RAMP_DOWN_TX1 |
b6a5e36de839
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parents:
diff
changeset
|
1361 // for the 2nd TX the RAMP is: RAMP_UP_TX2 / RAMP_DOWN_TX1 |
b6a5e36de839
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parents:
diff
changeset
|
1362 // for the 3rd TX the RAMP is: RAMP_UP_TX3 / RAMP_DOWN_TX2 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1363 // (...) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1364 // for the (i)th TX the RAMP is: RAMP_UP_TX_(i) / RAMP_DOWN_TX_(i-1) |
b6a5e36de839
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parents:
diff
changeset
|
1365 // for the additionnal RAMP : xxxx / RAMP_DOWN_TX_last |
b6a5e36de839
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parents:
diff
changeset
|
1366 |
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parents:
diff
changeset
|
1367 txpwr_ramp_up = txpwr[i+ts_conv]; // the ramp up is the current TX |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1368 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1369 if(last_TX == NO_TX) // specific case of the first TX |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1370 txpwr_ramp_down = txpwr[i+ts_conv]; // the ramp down is the current TX |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1371 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1372 txpwr_ramp_down = txpwr[last_TX+ts_conv]; // the ramp down is the previous TX |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1373 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1374 #if(RF_FAM == 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1375 #if(DSP == 38) || (DSP == 39) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1376 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx++][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1377 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1378 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1379 #if (CODE_VERSION != SIMULATION) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1380 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx++][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1381 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1382 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1383 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1384 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1385 // memorize the last TX window |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1386 last_TX = i; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1387 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1388 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1389 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1390 // program an interrupt in the TS following |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1391 // the last TX window and needed by the DSP |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1392 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1393 // Is it the TS following a TX window ? |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1394 #if 0 /* original LoCosto code */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1395 if((i == last_TX+1) && (i<8)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1396 #else /* FreeCalypso TCS211 reconstruction */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1397 if (i == last_TX+1) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1398 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1399 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1400 // program the interrupt |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1401 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = (1 << B_MS_RULE); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1402 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1403 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1404 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1405 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1406 // in a multi-TX case an additionnal ramp down must be set |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1407 if(cpt_TX > 1) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1408 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1409 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..] for slot i and set the interrupt |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1410 #if 0 /* FreeCalypso TCS211 reconstruction */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1411 if((last_TX+1) <= 7) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1412 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1413 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[last_TX+1] = ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_MS_RULE)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1414 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1415 // Store Ramp. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1416 // ========== |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1417 txpwr_ramp_up = txpwr[last_TX+ts_conv]; // this ramp up is unused (default: set to last_TX) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1418 txpwr_ramp_down = txpwr[last_TX+ts_conv]; // the ramp down is the last TX |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1419 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1420 #if(RF_FAM == 61) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1421 #if(DSP ==38) || (DSP == 39) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1422 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1423 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1424 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1425 #if (CODE_VERSION != SIMULATION) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1426 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1427 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1428 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1429 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1430 // #endif Locosto |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1431 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1432 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1433 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1434 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1435 /* l1pddsp_ul_ptcch_data() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1436 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1437 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1438 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1439 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1440 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1441 void l1pddsp_ul_ptcch_data(UWORD8 cs_type, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1442 UWORD16 channel_request_data, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1443 UWORD8 bsic, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1444 UWORD16 radio_freq, |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1445 UWORD8 timeslot_no) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1446 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1447 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1448 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1449 // UL on TS=timeslot_no. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1450 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> timeslot_no; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1451 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1452 // Swap I/Q management. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1453 swap_bit = l1ps_swap_iq_ul(radio_freq); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1454 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1455 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1456 // Set "b_ptcch_ul" to indicate PTCCH/UL to DSP. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1457 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= (1 << B_PTCCH_UL); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1458 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1459 // Store CS type. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1460 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[0] = cs_type; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1461 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1462 // Store UL data block. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1463 if(cs_type == CS_PAB8_TYPE) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1464 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1465 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[1] = ((API)(bsic << 2)) | |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1466 ((API)(channel_request_data) << 8); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1467 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[2] = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1468 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1469 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1470 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1471 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[1] = ((API)(channel_request_data) << 5); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1472 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[2] = ((API)(bsic << 10)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1473 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1474 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1475 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1476 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1477 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1478 /* l1pddsp_interf_meas_ctrl() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1479 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1480 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1481 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1482 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1483 void l1pddsp_interf_meas_ctrl(UWORD8 nb_meas_req) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1484 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1485 // Interference measurement task set as a monitoring task within GSM interface. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1486 // 101 means 1 meas, 102 means 2 meas ... |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1487 // Rem: swap I/Q is not managed for power measurements. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1488 l1s_dsp_com.dsp_db_w_ptr->d_task_md = INTERF_DSP_TASK + nb_meas_req; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1489 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1490 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1491 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1492 /*-------------------------------------------------------*/ |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1493 /* l1pddsp_transfer_meas_ctrl() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1494 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1495 /* Parameters : */ |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1496 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1497 /* Functionality : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1498 /*-------------------------------------------------------*/ |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1499 void l1pddsp_transfer_meas_ctrl(UWORD8 meas_position) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1500 { |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1501 // Store measurement position. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1502 // Rem: This is a L1S filtered information giving the position of the meas. as a |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1503 // bitmap. |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1504 // Rem: swap I/Q is not managed for power measurements. |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1505 l1ps_dsp_com.pdsp_db_w_ptr->d_task_pm_gprs = meas_position; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1506 } |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1507 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1508 /*-------------------------------------------------------*/ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1509 /* l1pddsp_meas_ctrl() */ |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1510 /*-------------------------------------------------------*/ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1511 /* Parameters : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1512 /* Return : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1513 /* Functionality : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1514 /*-------------------------------------------------------*/ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1515 void l1pddsp_meas_ctrl(UWORD8 nbmeas, UWORD8 pm_pos) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1516 { |
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src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1517 // Request Signal level measurement task to DSP. A bit map is passed |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1518 // to DSP in order to specify the position of the measurement. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1519 // Note: MSB is TN = 0 and LSB is TN = 7. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1520 // Rem: swap I/Q is not managed for power measurements. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1521 // Note: currently a maximum of four Pm can be performed / TDMA. This would |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1522 // be modified in a near futur. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1523 // Note: If a Rx is programmed i.e. pm_pos = 1, only a maximum |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1524 // of 3 Pm is requested to DSP and position of the Pm are right shifted (Rx on TN = 0). |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1525 // Remark: In packet Idle mode Rx are still on TN = 0. This implies three Pm |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1526 // always after the Rx. |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1527 l1ps_dsp_com.pdsp_db_w_ptr->d_task_pm_gprs = ((UWORD8) (0xff << (8 - nbmeas))) >> pm_pos; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1528 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1529 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1530 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1531 /* l1pddsp_meas_read() */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1532 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1533 /* Parameters : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1534 /* Return : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1535 /* Functionality : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1536 /*-------------------------------------------------------*/ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1537 void l1pddsp_meas_read(UWORD8 nbmeas, UWORD8 *a_pm) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1538 { |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1539 UWORD8 i = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1540 UWORD8 j; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1541 UWORD8 bit_mask = 0x80; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1542 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1543 // Looks for first PM position |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1544 while ((i < 8) && (l1ps_dsp_com.pdsp_db_r_ptr->d_task_pm_gprs & bit_mask) == 0) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1545 { |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1546 i++; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1547 bit_mask >>= 1; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1548 } |
b6a5e36de839
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parents:
diff
changeset
|
1549 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1550 // Read 'nbmeas' contiguous PM levels from the first PM position |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1551 // Note: PM are always programmed on contiguous timeslots |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1552 #if 0 /* original LoCosto code */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1553 for (j = 0; ((j < nbmeas)&&(i < 8)); j++) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1554 #else /* FreeCalypso TCS211 reconstruction */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1555 for (j = 0; j < nbmeas; j++) |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1556 #endif |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1557 { |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1558 // Download PM from DSP/MCU memory interface |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1559 a_pm[j] = (l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[i] & 0xffff) >> 5; |
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parents:
diff
changeset
|
1560 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1561 // Read next PM on following TN |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1562 i++; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1563 } |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1564 } |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1565 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1566 /*-------------------------------------------------------*/ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1567 /* l1pddsp_load_bcchn_task() */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1568 /*-------------------------------------------------------*/ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1569 /* Parameters : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1570 /* Return : */ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1571 /* Functionality : */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1572 /*-------------------------------------------------------*/ |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1573 void l1pddsp_load_bcchn_task(UWORD8 tsq,UWORD16 radio_freq ) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1574 { |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1575 UWORD16 swap_bit = l1ps_swap_iq_dl(radio_freq); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1576 |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1577 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NBN_DSP_TASK | (swap_bit << 15); // Load BCCHN task |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1578 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1579 } |
b6a5e36de839
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1580 #endif |