FreeCalypso > hg > fc-selenite
annotate src/cs/drivers/drv_core/clkm/clkm.c @ 163:a911ac771094
board preprocessor conditionals: prep for more FC hw in the future
Please see the corresponding change in fc-magnetite for the explanation.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 01 Apr 2019 01:20:03 +0000 |
parents | b6a5e36de839 |
children |
rev | line source |
---|---|
0
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 /****************************************************************************** |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 Property of Texas Instruments -- For Unrestricted Internal Use Only |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 Unauthorized reproduction and/or distribution is strictly prohibited. This |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 product is protected under copyright law and trade secret law as an |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 rights reserved. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 Filename : clkm.c |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 Description : Set of functions useful to test the Saturn |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 CLKM peripheral |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 Project : drivers |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 Author : pmonteil@tif.ti.com Patrice Monteil. |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
19 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
20 Version number : 1.13 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
21 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
22 Date : 05/23/03 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
23 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
24 Previous delta : 10/23/01 14:43:31 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
25 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
26 Sccs Id (SID) : '@(#) clkm.c 1.11 10/23/01 14:43:31 ' |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
27 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
28 *****************************************************************************/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
29 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
30 //############################################################ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
31 //############################################################ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
32 //### Be careful: this file must be placed in Flash Memory ### |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
33 //### and compiled in 16 bits length intructions ### |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
34 //### (CF. the function wait_ARM_cycles() ### |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
35 //############################################################ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
36 //############################################################ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
37 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
38 #include "l1sw.cfg" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
39 #include "chipset.cfg" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
40 #include "board.cfg" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
41 #include "swconfig.cfg" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
42 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
43 #if (OP_L1_STANDALONE == 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
44 #include "main/sys_types.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
45 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
46 #include "sys_types.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
47 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
48 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
49 #include "clkm.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
50 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
51 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
52 #if (CHIPSET == 12) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
53 #include "sys_memif.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
54 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
55 #include "memif/mem.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
56 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
57 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
58 #if (BOARD == 34) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
59 #include "armio/armio.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
60 #include "timer/timer.h" |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
61 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
62 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
63 static SYS_UWORD32 ratio_wait_loop = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
64 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
65 #if (CHIPSET == 12) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
66 const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE] = {1, 1.5, 2, 3}; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
67 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
68 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
69 #if (BOARD == 34) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
70 /* |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
71 * CLKM_InitARMClock() |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
72 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
73 * This init is for VTCX0 = 13 MHz |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
74 * (use CLKM_VTCXO_26 if VTCX0 is 26 MHz) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
75 * Parameters : src : 0x0 means EXT CLK (mpu dpll) selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
76 * 0x1 means VTCX0 selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
77 * div : Division factor applied to clock |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
78 * source |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
79 * (div = 3 -> divise by 3/2 in fact) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
80 * WARNING : reverse order in comparison to ULYSSE |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
81 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
82 * Return : none |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
83 * Functionality :Initialize the ARM Clock frequency |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
84 */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
85 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
86 void CLKM_InitARMClock(int src, int div) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
87 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
88 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
89 int clk_xp5, clk_div; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
90 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
91 if (div == 3) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
92 clk_xp5 = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
93 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
94 clk_xp5 = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
95 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
96 if (div == 2) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
97 clk_div = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
98 else if (div == 4) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
99 clk_div = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
100 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
101 clk_div = 3; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
102 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
103 cntl &= ~(MASK_ARM_MCLK_1P5 | CLKM_MCLK_DIV); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
104 cntl |= ((clk_xp5 << 3) | (clk_div << 4)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
105 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
106 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 if (src) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 CLKM_EnableDPLL(0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
110 CLKM_EnableDPLL(1); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 /* |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 * CLKM_SetMclkDiv |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 * Set divider |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 * Parameter : 2-bit divider as per spec (0-7) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 * Side-effect : compute magic delay for busy loops |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
121 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
123 void CLKM_SetMclkDiv(int div) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
125 volatile SYS_UWORD16 clkm_ctrl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 clkm_ctrl = *((volatile SYS_UWORD16 *) CLKM_ARM_CLK); // read register |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
127 clkm_ctrl &= ~CLKM_MCLK_DIV; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 clkm_ctrl |= (div << 4); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
129 *((volatile SYS_UWORD16 *) CLKM_ARM_CLK) = clkm_ctrl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
132 /* |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 * CLKM_EnableDPLL |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 * Enable or disable 48mhz PLL for ARM clock |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 * Parameter : 1 or 0 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 * Side-effect : compute magic delay for busy loops |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 void CLKM_EnableDPLL(int enable) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 volatile SYS_UWORD16 clkm_ctrl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 // read CLKM register |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 clkm_ctrl = *((volatile SYS_UWORD16 *) CLKM_ARM_CLK); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 if (enable) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 // PARAMETERS tuned for the AVENGER 2 reference design |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 // we wait before accessing external memory at wake up |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 // we have 2.5 ms margin before the first IT TDMA, we wait |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 // |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 // 5000 loop cycles |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 // 5000 * 5 arm7 cycles |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 // giving <= 1 ms at 26 MHz |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 // |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 wait_ARM_cycles(5000); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 // reset bit for VTCXO |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 clkm_ctrl &= ~CLKM_CLKIN_SEL; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 *((volatile SYS_UWORD16 *) CLKM_ARM_CLK) = clkm_ctrl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 // disable clk48mhz |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 AI_ResetBit(6); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 /* |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 * CLKM_EnableSharedMemClock |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 * Enable or disable shared mem clock |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 * Parameter : 1 or 0 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 void CLKM_EnableSharedMemClock(int enable) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 if (enable) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 // request shared mem clock and wait for MPU HW acknowledge |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 AI_ResetBit(4); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 while(AI_ReadBit(5)!=1); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 // disable shared mem clock |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 AI_SetBit(4); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 /* |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 * CLKM_InitLeadClock |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 * Parameter : onoff, mul, ndiv, div |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 * onoff -> (1:pll on) (0: pll off) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 * if div = 0 -> x(plmul+1) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
202 * if div = 1 -> x(plmul+1)/2 if plmul is even |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 * x(plmul/4) if plmul is odd |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 * ndiv |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 void CLKM_InitLeadClock(int onoff, int mul, int ndiv, int div) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 int pldiv, pllndiv ; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 SYS_UWORD16 value = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 value |= onoff & CLKM_PLONOFF ; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 value |= (mul << 1) & CLKM_PLMUL; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 value |= (ndiv << 5)& CLKM_PLLNDIV; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
215 value |= (div << 6) & CLKM_PLDIV; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
217 CLKM_INITLEADPLL(value); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
218 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
219 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
220 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
221 /*--------------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
222 /* CLKM_InitARMClock() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
223 /*--------------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
224 /* Parameters : clk_src : 0x00 means DPLL selected */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
225 /* 0x01 means VTCX0 selected */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
226 /* 0x03 means CLKIN selected */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
227 /* clk_xp5 : Enable 1.5 or 2.5 division factor */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
228 /* (0 or 1) */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
229 /* clk_div : Division factor applied to clock */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
230 /* source */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
231 /* WARNING : reverse order in comparison to ULYSSE */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
232 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
233 /* Return : none */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
234 /* Functionality :Initialize the ARM Clock frequency */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
235 /*--------------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
236 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
237 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
238 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
239 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
240 cntl &= ~(CLKM_CLKIN0 | CLKM_CLKIN_SEL | CLKM_ARM_MCLK_XP5 | CLKM_MCLK_DIV); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
241 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
242 cntl |= ((clk_src << 1) | (clk_xp5 << 3) | (clk_div << 4)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
243 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
244 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
245 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
246 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
247 /*-------------------------------------------------------------- |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
248 * CLKM_InitARMClock() |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
249 *-------------------------------------------------------------- |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
250 * Parameters : clk_src : 0x00 means CLKIN selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
251 * 0x01 means 32 K selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
252 * 0x02 means External clock selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
253 * |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
254 * Return : none |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
255 * Functionality :Initialize the ARM Clock frequency |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
256 *--------------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
257 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
258 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
259 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
260 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 cntl &= ~(CLKM_LOW_FRQ | CLKM_CLKIN_SEL | CLKM_MCLK_DIV); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
262 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
263 cntl |= ((clk_src << 1) | (clk_div << 4)); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
264 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
265 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
266 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
267 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
269 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
270 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
271 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
272 /* convert_nanosec_to_cycles() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
274 /* parameter: time in 10E-9 seconds */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
275 /* return: Number of cycles for the wait_ARM_cycles() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 /* function */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 /* Description: */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
279 /* ------------ */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280 /* convert x nanoseconds in y cycles used by the ASM loop*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 /* function . Before calling this function, call the */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
282 /* initialize_wait_loop() function */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
283 /* Called when the HardWare needs time to wait */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
284 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285 SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
287 return( time / ratio_wait_loop); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
288 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
290 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
292 /* initialize_wait_loop() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
293 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 /* Description: */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 /* ------------ */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
297 /* Init the ratio used to convert time->Cycles according */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
298 /* to hardware parameters */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
299 /* measurement time for this function (ARM 39Mhz, 3 waits*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
300 /* states) = 75 micoseconds */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
301 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
302 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 void initialize_wait_loop(void) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
304 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 #if (BOARD == 34) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
306 unsigned long ulTimeSpent=0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
308 // set up timer 2 for wait_ARM_cycles function calibration |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 TM_EnableTimer (2); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 TM_ResetTimer (2, 0xFFFF, 0, 0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 // run wait_ARM_cycles() for 10000 loops |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
313 wait_ARM_cycles(10000); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
315 // time spent expressed in timer cycles |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
316 // where 1 timer cycle = 2462 ns with prescale 0 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
317 // 13 MHz divided by 16 = timer clkin |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
318 // prescale 0 -> divided by 2 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
319 ulTimeSpent = TM_ReadTimer (2); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
320 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
321 TM_StopTimer (2); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
322 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
323 ulTimeSpent = 0xFFFF - ulTimeSpent; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
324 ulTimeSpent *= 2462; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
325 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
326 // compute ratio_wait_loop |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
327 ratio_wait_loop = (unsigned long)(ulTimeSpent/10000.); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
328 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
329 #define NBR_CYCLES_IN_LOOP 5 // this value is got from an oscilloscope measurement |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
330 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
331 double src_ratio; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
332 double final_ratio; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
333 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
334 SYS_UWORD16 flash_access_size; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
335 SYS_UWORD16 flash_wait_state; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
336 SYS_UWORD32 nbr; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
337 SYS_UWORD32 arm_clock; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
338 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
339 ////////////////////////////////// |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
340 // compute the ARM clock used // |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
341 ////////////////////////////////// |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
342 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
343 SYS_UWORD16 arm_mclk_xp5; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
344 SYS_UWORD16 arm_ratio; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
345 SYS_UWORD16 clk_src; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
346 SYS_UWORD16 clkm_cntl_arm_clk_reg = * (volatile SYS_UWORD16 *) CLKM_CNTL_ARM_CLK; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
347 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
348 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
349 clk_src = (clkm_cntl_arm_clk_reg & MASK_CLKIN) >> 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
350 switch (clk_src) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
351 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
352 case 0x00: //DPLL selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
353 // select the DPLL factor |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
354 #if (CHIPSET == 12) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
355 if (((* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_LOCK) != 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
356 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
357 if (((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK) != 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
358 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
359 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
360 SYS_UWORD16 dpll_div; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
361 SYS_UWORD16 dpll_mul; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
362 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
363 dpll_div=DPLL_READ_DPLL_DIV; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
364 dpll_mul=DPLL_READ_DPLL_MUL; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
365 src_ratio = (double)(dpll_mul)/(double)(dpll_div+1); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
366 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
367 else // DPLL in bypass mode |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
368 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
369 SYS_UWORD16 dpll_div = DPLL_BYPASS_DIV; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
370 src_ratio= (double)(1)/(double)(dpll_div+1); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
371 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
372 break; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
373 case 0x01: //VTCX0 selected |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
374 src_ratio = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
375 break; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
376 case 0x03: //CLKIN selected (external clock) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
377 src_ratio = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
378 break; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
379 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
380 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
381 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
382 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
383 // check if the 1.5 or 2.5 division factor is enabled |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
384 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & CLKM_ARM_MCLK_XP5; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
385 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
386 if (arm_mclk_xp5 == 0) // division factor enable for ARM clock ? |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
387 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
388 if (arm_ratio == 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
389 arm_ratio =1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
390 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
391 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
392 arm_ratio = ((arm_ratio>>1) & 0x0001) == 0 ? 1.5 : 2.5; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
393 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
394 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
395 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
396 src_ratio = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
397 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
398 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
399 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
400 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
401 // check if the 1.5 or 2.5 division factor is enabled |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
402 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & MASK_ARM_MCLK_1P5; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
403 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
404 if (arm_mclk_xp5 == 1) // division factor enable for ARM clock ? |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
405 arm_ratio = 1.5; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
406 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
407 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
408 if (arm_ratio == 0) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
409 arm_ratio = 4; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
410 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
411 if (arm_ratio == 1 ) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
412 arm_ratio = 2; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
413 else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
414 arm_ratio = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
415 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
416 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
417 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
418 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
419 final_ratio = (src_ratio / (double) arm_ratio); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
420 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
421 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
422 ////////////////////////////////////////// |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
423 // compute the Flash wait states used // |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
424 ////////////////////////////////////////// |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
425 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
426 #if (CHIPSET == 12) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
427 flash_access_size = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
428 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
429 flash_access_size = *((volatile SYS_UWORD16 *) MEM_REG_nCS0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
430 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
431 flash_access_size = (flash_access_size >> 5) & 0x0003; // 0=>8bits, 1=>16 bits, 2 =>32 bits |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
432 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
433 // the loop file is compiled in 16 bits it means |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
434 // flash 8 bits => 2 loads for 1 16 bits assembler instruction |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
435 // flash 16 bits => 1 loads for 1 16 bits assembler instruction |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
436 // flash/internal RAM 32 bits => 1 loads for 1 16 bits assembler instruction (ARM bus 16 bits !!) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
437 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
438 // !!!!!!!!! be careful: if this file is compile in 32 bits, change these 2 lines here after !!! |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
439 if (flash_access_size == 0) flash_access_size = 2; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
440 else flash_access_size = 1; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
441 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
442 #if (CHIPSET == 12) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
443 /* |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
444 * loop move to run in internal memory, due to page mode in external memory |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
445 */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
446 flash_wait_state = 0; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
447 #else |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
448 flash_wait_state = *((volatile SYS_UWORD16 *) MEM_REG_nCS0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
449 flash_wait_state &= 0x001F; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
450 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
451 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
452 ////////////////////////////////////// |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
453 // compute the length of the loop // |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
454 ////////////////////////////////////// |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
455 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
456 // Number of flash cycles for the assembler loop |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
457 nbr = NBR_CYCLES_IN_LOOP; |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
458 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
459 // Number of ARM cycles for the assembler loop |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
460 nbr = nbr * (flash_wait_state + 1) * (flash_access_size); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
461 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
462 // time for the assembler loop (unit nanoseconds: 10E-9) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
463 arm_clock = final_ratio * 13; // ARM clock in Mhz |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
464 ratio_wait_loop = (SYS_UWORD32)((nbr*1000) / arm_clock); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
465 #endif |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
466 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
467 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
468 #if (CHIPSET != 12) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
469 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
470 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
471 /* wait_ARM_cycles() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
472 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
473 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
474 /* Description: */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
475 /* ------------ */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
476 /* Called when the HardWare needs time to wait. */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
477 /* this function wait x cycles and is used with the */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
478 /* convert_nanosec_to_cycles() & initialize_wait_loop() */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
479 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
480 /* Exemple: wait 10 micro seconds: */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
481 /* initialize_wait_loop(); */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
482 /* wait_ARM_cycles(convert_nanosec_to_cycles(10000)) */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
483 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 /* minimum time value with cpt_loop = 0 (estimated) */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485 /* and C-SAMPLE / flash 6,5Mhz ~ 1,5 micro seconds */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
486 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 /* */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
488 /* Be careful : in order to respect the rule about the */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
489 /* conversion "time => number of cylcles in this loop" */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
490 /* (Cf the functions: convert_nanosec_to_cycles() and */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
491 /* initialize_wait_loop() ) respect the following rules: */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 /* This function must be placed in Flash Memory and */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 /* compiled in 16 bits instructions length */ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
494 /*-------------------------------------------------------*/ |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 void wait_ARM_cycles(SYS_UWORD32 cpt_loop) |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
496 { |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
497 // C code: |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
498 // while (cpt_loop -- != 0); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
499 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
500 asm(" CMP A1, #0"); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
501 asm(" BEQ END_FUNCTION"); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
502 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 asm("LOOP_LINE: "); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504 asm(" SUB A1, A1, #1"); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 asm(" CMP A1, #0"); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
506 asm(" BNE LOOP_LINE"); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 asm("END_FUNCTION: "); |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 } |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 |
b6a5e36de839
src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511 #endif /* (CHIPSET != 12)*/ |