FreeCalypso > hg > fc-selenite
annotate src/cs/drivers/drv_core/inth/sys_inth.h @ 163:a911ac771094
board preprocessor conditionals: prep for more FC hw in the future
Please see the corresponding change in fc-magnetite for the explanation.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 01 Apr 2019 01:20:03 +0000 |
parents | b6a5e36de839 |
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rev | line source |
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1 /* @(#) nom : sys_inth.h SID: 1.2 date : 05/23/03 */ |
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2 /* Filename: sys_inth.h */ |
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3 /* Version: 1.2 */ |
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4 /****************************************************************************** |
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5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT |
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6 * |
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7 * (C) 2002 Texas Instruments France. All rights reserved |
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8 * |
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9 * Author : Francois AMAND |
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10 * |
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11 * |
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12 * Important Note |
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13 * -------------- |
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14 * |
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15 * This S/W is a preliminary version. It contains information on a product |
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16 * under development and is issued for evaluation purposes only. Features |
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17 * characteristics, data and other information are subject to change. |
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18 * |
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19 * The S/W is furnished under Non Disclosure Agreement and may be used or |
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20 * copied only in accordance with the terms of the agreement. It is an offence |
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21 * to copy the software in any way except as specifically set out in the |
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22 * agreement. No part of this document may be reproduced or transmitted in any |
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23 * form or by any means, electronic or mechanical, including photocopying and |
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24 * recording, for any purpose without the express written permission of Texas |
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25 * Instruments Inc. |
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26 * |
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27 ****************************************************************************** |
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28 * |
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29 * FILE NAME: sys_inth.h |
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30 * |
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31 * |
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32 * PURPOSE: Header file for the Interrupt Handler Driver. |
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33 * |
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34 * |
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35 * FILE REFERENCES: |
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36 * |
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37 * Name IO Description |
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38 * ------------- -- --------------------------------------------- |
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39 * |
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40 * |
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41 * |
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42 * EXTERNAL VARIABLES: |
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43 * |
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44 * Source: |
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45 * |
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46 * Name Type IO Description |
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47 * ------------- --------------- -- ------------------------------ |
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48 * |
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49 * |
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50 * |
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51 * EXTERNAL REFERENCES: |
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52 * |
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53 * Name Description |
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54 * ------------------ ------------------------------------------------------- |
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55 * |
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56 * |
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57 * |
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58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES: |
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59 * |
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60 * |
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61 * |
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62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS: |
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63 * |
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64 * |
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65 * |
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66 * NOTES: |
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67 * |
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68 * |
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69 * |
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70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES: |
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71 * |
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72 * |
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73 * |
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74 * |
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75 * DEVELOPMENT HISTORY: |
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76 * |
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77 * Date Name(s) Version Description |
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78 * ----------- -------------- ------- ------------------------------------- |
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79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation |
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80 * |
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81 * ALGORITHM: |
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82 * |
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83 * |
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84 *****************************************************************************/ |
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85 |
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86 #include "l1sw.cfg" |
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87 #include "chipset.cfg" |
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88 |
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89 #if (CHIPSET == 12) |
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90 |
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91 #ifndef __SYS_INTH_H__ |
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92 #define __SYS_INTH_H__ |
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93 |
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94 #if (OP_L1_STANDALONE == 0) |
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95 #include "main/sys_types.h" |
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96 #else |
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97 #include "sys_types.h" |
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98 #endif |
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99 #include "sys_map.h" |
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100 |
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101 |
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102 /* |
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103 * Driver version |
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104 */ |
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105 #define C_INTH_DRIVER_VERSION 0x0001 |
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106 |
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107 |
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108 /* |
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109 * Number of interrupts |
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110 */ |
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111 #define C_INTH_NUM_INT 32 |
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112 #define C_INTH_2ND_NUM_INT 5 |
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113 |
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114 #define C_INTH_NB_INTERRUPT (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT) |
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115 |
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116 |
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117 /* |
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118 * Main INTH : Interrupt bit numbers |
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119 */ |
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120 #define C_INTH_WATCHDOG_IT 0 |
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121 #define C_INTH_TIMER1_IT 1 |
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122 #define C_INTH_TIMER2_IT 2 |
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123 #define C_INTH_TSP_RECEIVE_IT 3 |
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124 #define C_INTH_FRAME_IT 4 |
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125 #define C_INTH_PAGE_IT 5 |
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126 #define C_INTH_SIM_IT 6 |
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127 #define C_INTH_UART_MODEM1_IT 7 |
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128 #define C_INTH_KEYBOARD_IT 8 |
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129 #define C_INTH_RTC_TIMER_IT 9 |
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130 #define C_INTH_RTC_ALARM_IT 10 |
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131 #define C_INTH_ULPD_GAUGING_IT 11 |
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132 #define C_INTH_ABB_IRQ_IT 12 |
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133 #define C_INTH_SPIv 13 |
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134 #define C_INTH_DMA_IT 14 |
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135 #define C_INTH_API_IT 15 |
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136 #define C_INTH_GPIO_IT 16 |
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137 #define C_INTH_ABB_FIQ_IT 17 |
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138 #define C_INTH_UART_IRDA_IT 18 |
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139 #define C_INTH_TGSM_IT 19 |
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140 #define C_INTH_GEA_IT 20 |
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141 #define C_INTH_EXT_IRQ1_IT 21 |
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142 #define C_INTH_EXT_IRQ2_IT 22 |
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143 #define C_INTH_USIM_CD_IT 23 |
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144 #define C_INTH_USIM_IT 24 |
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145 #define C_INTH_LCD_IT 25 |
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146 #define C_INTH_USB_IT 26 |
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147 #define C_INTH_MMC_SD_MS_IT 27 |
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148 #define C_INTH_UART_MODEM2_IT 28 |
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149 #define C_INTH_2ND_INTH_IT 29 |
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150 #define C_INTH_I2C_IT 30 |
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151 #define C_INTH_NAND_FLASH_IT 31 |
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152 |
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153 /* |
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154 * Second INTH : Interrupt bit numbers |
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155 */ |
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156 #define C_INTH_RNG_IT 32 |
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157 #define C_INTH_SHA1_MD5_IT 33 |
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158 #define C_INTH_EMPU_IT 34 |
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159 #define C_INTH_SEC_DMA_IT 35 |
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160 #define C_INTH_SEC_TIMER_IT 36 |
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161 |
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162 |
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163 /* |
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164 * Address of the Main interrupt handler registers |
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165 */ |
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166 #define C_INTH_IT_REG1 C_MAP_INTH_BASE /* INTH IT register 1 */ |
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167 #define C_INTH_IT_REG2 (C_MAP_INTH_BASE + 0x02) /* INTH IT register 2 */ |
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168 #define C_INTH_MASK_REG1 (C_MAP_INTH_BASE + 0x08) /* INTH mask register 1 */ |
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169 #define C_INTH_MASK_REG2 (C_MAP_INTH_BASE + 0x0a) /* INTH mask register 2 */ |
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170 #define C_INTH_B_IRQ_REG (C_MAP_INTH_BASE + 0x10) /* INTH source binary IRQ reg. */ |
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171 #define C_INTH_B_FIQ_REG (C_MAP_INTH_BASE + 0x12) /* INTH source binary FIQ reg. */ |
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172 #define C_INTH_CTRL_REG (C_MAP_INTH_BASE + 0x14) /* INTH control register */ |
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173 #define C_INTH_EXT_REG (C_MAP_INTH_BASE + 0x20) /* INTH 1st external int. reg. */ |
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174 |
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175 /* |
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176 * Address of the Second interrupt handler registers |
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177 */ |
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178 #define C_INTH2_IT_REG1 C_MAP_INTH_SEC_BASE /* INTH IT register 1 */ |
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179 #define C_INTH2_MASK_REG1 (C_MAP_INTH_SEC_BASE + 0x08) /* INTH mask register 1 */ |
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180 #define C_INTH2_B_IRQ_REG (C_MAP_INTH_SEC_BASE + 0x10) /* INTH source binary IRQ reg. */ |
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181 #define C_INTH2_CTRL_REG (C_MAP_INTH_SEC_BASE + 0x14) /* INTH control register */ |
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182 #define C_INTH2_EXT_REG (C_MAP_INTH_SEC_BASE + 0x20) /* INTH 1st external int. reg. */ |
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183 |
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184 |
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185 /* |
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186 * INTH_B_x_REG definition |
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187 */ |
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188 #define C_INTH_SRC_NUM 0x001f |
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189 #define C_INTH2_SRC_NUM 0x0007 |
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190 |
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191 /* |
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192 * ILR_IRQx_REG definition |
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193 */ |
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194 #define C_INTH_IRQ 0 |
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195 #define C_INTH_FIQ 1 |
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196 |
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197 #define C_INTH_LEVEL 0 |
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198 #define C_INTH_EDGE 1 |
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199 |
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200 |
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201 |
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202 /**************************************************************************** |
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203 * MACRO DEFINITION |
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204 ***************************************************************************/ |
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205 |
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206 /**************************************************************************** |
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207 * |
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208 * MACRO NAME: F_INTH_ENABLE_ONE_IT |
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209 * Enable the interrupt specified in argument. |
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210 * |
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211 * |
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212 * ARGUMENT LIST: |
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213 * |
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214 * Argument Description |
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215 * ------------ ---------------------------------------------------------- |
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216 * d_it Interrupt index |
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217 * |
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218 * RETURN VALUE: None |
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219 * |
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220 ***************************************************************************/ |
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221 |
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222 #define F_INTH_ENABLE_ONE_IT(d_it) { \ |
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223 if (d_it < 16) \ |
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224 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 &= ~(1 << d_it); \ |
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225 else if (d_it < C_INTH_NUM_INT) \ |
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226 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 &= ~(1 << (d_it-16)); \ |
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227 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \ |
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228 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 &= ~(1 << (d_it-32)); \ |
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229 } |
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230 |
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231 |
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232 |
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233 /**************************************************************************** |
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234 * |
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235 * MACRO NAME: F_INTH_DISABLE_ONE_IT |
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236 * Disable the interrupt specified in argument. |
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237 * |
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238 * |
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239 * ARGUMENT LIST: |
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240 * |
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241 * Argument Description |
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242 * ------------ ---------------------------------------------------------- |
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243 * d_it Interrupt index |
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244 * |
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245 * RETURN VALUE: None |
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246 * |
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247 ***************************************************************************/ |
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248 |
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249 #define F_INTH_DISABLE_ONE_IT(d_it) { \ |
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250 if (d_it < 16) \ |
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251 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 |= (1 << d_it); \ |
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252 else if (d_it < C_INTH_NUM_INT) \ |
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253 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 |= (1 << (d_it-16)); \ |
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254 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \ |
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255 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 |= (1 << (d_it-32)); \ |
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256 } |
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257 |
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258 |
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259 |
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260 /**************************************************************************** |
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261 * |
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262 * MACRO NAME: F_INTH_DISABLE_ALL_IT |
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263 * Disable all interrupts. |
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264 * |
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265 * |
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266 * ARGUMENT LIST: |
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267 * |
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268 * Argument Description |
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269 * ------------ ---------------------------------------------------------- |
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270 * |
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271 * RETURN VALUE: None |
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272 * |
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273 ***************************************************************************/ |
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274 |
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275 #define F_INTH_DISABLE_ALL_IT { \ |
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276 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 = 0xffff; \ |
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277 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 = 0xffff; \ |
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278 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 = 0x001f; \ |
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279 } |
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280 |
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281 |
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282 |
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283 /**************************************************************************** |
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284 * |
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285 * MACRO NAME: F_INTH_RESET_ALL_IT |
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286 * Reset all interrupts. |
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287 * |
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288 * |
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289 * ARGUMENT LIST: |
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290 * |
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291 * Argument Description |
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292 * ------------ ---------------------------------------------------------- |
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293 * |
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294 * RETURN VALUE: None |
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295 * |
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296 ***************************************************************************/ |
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297 |
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298 #define F_INTH_RESET_ALL_IT { \ |
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299 * (volatile SYS_UWORD16 *) C_INTH_IT_REG1 &= 0x0000; \ |
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300 * (volatile SYS_UWORD16 *) C_INTH_IT_REG2 &= 0x0000; \ |
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301 * (volatile SYS_UWORD16 *) C_INTH2_IT_REG1 &= 0x0000; \ |
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302 } |
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303 |
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304 |
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305 /**************************************************************************** |
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306 * |
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307 * MACRO NAME: F_INTH_RESET_ONE_IT |
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308 * Reset the interrupt specified in argument. |
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309 * |
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310 * |
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311 * ARGUMENT LIST: |
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312 * |
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313 * Argument Description |
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314 * ------------ ---------------------------------------------------------- |
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315 * d_it Interrupt index |
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316 * |
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317 * RETURN VALUE: None |
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318 * |
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319 ***************************************************************************/ |
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320 |
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321 #define F_INTH_RESET_ONE_IT(d_it) { \ |
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322 if (d_it < 16) \ |
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323 * (volatile SYS_UWORD16 *) C_INTH_IT_REG1 &= ~(1 << d_it); \ |
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324 else if (d_it < C_INTH_NUM_INT) \ |
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325 * (volatile SYS_UWORD16 *) C_INTH_IT_REG2 &= ~(1 << (d_it-16)); \ |
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326 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \ |
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327 * (volatile SYS_UWORD16 *) C_INTH2_IT_REG1 &= ~(1 << (d_it-32)); \ |
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328 } |
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329 |
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330 /**************************************************************************** |
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331 * |
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332 * MACRO NAME: F_INTH_VALID_NEXT |
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333 * Valid next interrupt on the main interrupt handler. |
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334 * |
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335 * |
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336 * ARGUMENT LIST: |
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337 * |
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338 * Argument Description |
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339 * ------------ ---------------------------------------------------------- |
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340 * d_fiq_nirq Source of the interrupt IRQ or FIQ |
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341 * |
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342 * RETURN VALUE: None |
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343 * |
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344 ***************************************************************************/ |
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345 |
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346 #define F_INTH_VALID_NEXT(d_fiq_nirq) * (volatile SYS_UWORD16 *) C_INTH_CTRL_REG |= (1 << d_fiq_nirq) |
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347 |
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348 |
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349 |
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350 /**************************************************************************** |
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351 * |
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352 * MACRO NAME: F_INTH2_VALID_NEXT |
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353 * Valid next interrupt on the 2nd level interrupt handler. |
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354 * |
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355 * |
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356 * ARGUMENT LIST: |
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357 * |
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358 * Argument Description |
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359 * ------------ ---------------------------------------------------------- |
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360 * d_fiq_nirq Source of the interrupt IRQ or FIQ. |
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361 * |
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362 * RETURN VALUE: None |
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363 * |
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364 ***************************************************************************/ |
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365 |
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366 #define F_INTH2_VALID_NEXT(d_fiq_nirq) * (volatile SYS_UWORD16 *) C_INTH2_CTRL_REG |= (1 << d_fiq_nirq) |
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367 |
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368 |
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369 |
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370 /**************************************************************************** |
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371 * |
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372 * MACRO NAME: F_INTH_GET_IRQ |
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373 * Return pending IRQ interrupt index on the main interrupt handler. |
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374 * |
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375 * |
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376 * ARGUMENT LIST: |
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377 * |
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378 * Argument Description |
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379 * ------------ ---------------------------------------------------------- |
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380 * |
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381 * RETURN VALUE: IRQ interrupt index |
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382 * |
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383 ***************************************************************************/ |
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384 |
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385 #define F_INTH_GET_IRQ ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM) |
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386 |
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387 |
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388 |
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389 /**************************************************************************** |
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390 * |
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391 * MACRO NAME: F_INTH_GET_FIQ |
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392 * Return pending FIQ interrupt index on the main interrupt handler. |
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393 * |
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394 * |
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395 * ARGUMENT LIST: |
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396 * |
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397 * Argument Description |
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398 * ------------ ---------------------------------------------------------- |
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399 * |
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400 * RETURN VALUE: FIQ interrupt index |
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401 * |
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402 ***************************************************************************/ |
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403 |
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404 #define F_INTH_GET_FIQ ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM) |
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405 |
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406 |
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407 |
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408 /**************************************************************************** |
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409 * |
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410 * MACRO NAME: F_INTH2_GET_IRQ |
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411 * Return pending IRQ interrupt index on the 2nd level interrupt handler. |
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412 * |
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413 * |
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414 * ARGUMENT LIST: |
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415 * |
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416 * Argument Description |
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417 * ------------ ---------------------------------------------------------- |
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418 * |
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419 * RETURN VALUE: FIQ interrupt index |
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420 * |
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421 ***************************************************************************/ |
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422 |
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423 #define F_INTH2_GET_IRQ ((* (SYS_UWORD16 *) C_INTH2_B_IRQ_REG) & C_INTH2_SRC_NUM) |
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424 |
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425 |
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426 |
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427 /**************************************************************************** |
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428 * STRUCTURE DEFINITION |
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429 ***************************************************************************/ |
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430 |
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431 typedef struct { |
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432 SYS_UWORD8 d_fiq_nirq; |
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433 SYS_UWORD8 d_edge_nlevel; |
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434 SYS_UWORD8 d_priority; |
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435 SYS_FUNC d_it_handler; |
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436 } T_INTH_CONFIG; |
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437 |
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438 |
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439 |
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440 /**************************************************************************** |
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441 * GLOBAL VARIABLES REFERENCE |
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442 ***************************************************************************/ |
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443 |
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444 extern SYS_FUNC a_inth_it_handlers[C_INTH_NUM_INT][2]; |
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445 extern SYS_FUNC a_inth2_irq_handlers[C_INTH_2ND_NUM_INT]; |
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446 |
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447 |
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448 /**************************************************************************** |
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449 * PROTOTYPE DEFINITION |
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450 ***************************************************************************/ |
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451 |
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452 /* |
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453 * 16-BIS functions |
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454 */ |
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455 extern void f_inth_setup(T_INTH_CONFIG *p_inth_config); |
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456 extern SYS_UWORD16 f_inth_get_version(void); |
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457 |
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458 /* |
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459 * 32-BIS functions |
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460 */ |
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461 extern void f_inth_dummy(void); |
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462 extern void f_inth_irq_handler(void); |
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463 extern void f_inth_fiq_handler(void); |
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464 extern void f_inth_2nd_level_handler(void); |
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465 |
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466 #endif /* __SYS_INTH_H__ */ |
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467 |
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468 #endif /* (CHIPSET == 12) */ |