fc-selenite: src/cs/drivers/drv_app/uart/uartfax.c annotate

author	Mychaela Falconia <falcon@freecalypso.org>
date	Mon, 16 Jul 2018 23:56:58 +0000 (2018-07-16)
parents	397e3a3274ea
children	7409b22cac61

rev	line source
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*******************************************************************************
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * UARTFAX.C
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * This driver allows to control the UARTs of chipset 1.5 for fax and data
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * services. It performs flow control: RTS/CTS, XON/XOFF.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 * On C & D-Sample, DCD and DTR signals are supported on UART modem only with 2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 * I/Os.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 * On E-Sample, DCD and DTR signals are directly handled by Calypso+.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 * On Calypso, RTS and CTS are supported on both UARTs.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 * On Calypso+, RTS and CTS are supported on UART Modem1 & IrDA. UART Modem2 is
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 * not available through DB9 connector on E-Sample.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 * (C) Texas Instruments 1999 - 2003
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 ******************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 * E-Sample
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 * UART Modem1 UART Irda
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 * DB9 Calypso+ DB9 Calypso+
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 * 1 DCD DCD output 1 1, 6 and 4 are connected together on DB9
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 * 2 RX TX output 2 RX TX2 output
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 * 3 TX RX input 3 TX RX2 input
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 * 4 DTR DSR input 4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 * 5 GND 5 GND
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 * 6 NC 6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 * 7 RTS CTS input 7 RTS CTS2 input
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 * 8 CTS RTS output 8 CTS RTS2 output
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 * 9 NC 9 NC
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 * C & D-Sample
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 * UART Modem UART Irda
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 * DB9 Calypso DB9 Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 * 1 DCD I/O 2 output 1 1, 6 and 4 are connected together on DB9
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 * 2 RX TX output 2 RX TX2 output
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 * 3 TX RX input 3 TX RX2 input
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 * 4 DTR I/O 3 input 4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 * 5 GND 5 GND
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 * 6 NC 6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 * 7 RTS CTS input 7 RTS CTS2 input
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 * 8 CTS RTS output 8 CTS RTS2 output
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56 * 9 NC 9 NC
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 * B-Sample
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 * UART Modem UART Irda
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 * DB9 Ulysse DB9 Ulysse
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 * 1 1, 6 and 4 are connected together on DB9 (Modem and Irda)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 * 2 RX TX 2 RX TX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 * 3 TX RX 3 TX RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 * 4 4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 * 5 GND 5 GND
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 * 6 6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 * 7 RTS CTS 7 7 and 8 are connected together on DB9
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 * 8 CTS RTS 8
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 * 9 NC 9 NC
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #include "swconfig.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #include "l1sw.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 #if (OP_L1_STANDALONE == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 #include "rv.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #include "board.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #include "chipset.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 #ifdef BLUETOOTH_INCLUDED
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #include "btemobile.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 #include "fc-target.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 #include <string.h>
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #include "nucleus.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98 #include "main/sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 #include "faxdata.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #include "uartfax.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103 * Needed to reset and restart the sleep timer in case of incoming characters.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #include "serialswitch.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107 extern SYS_BOOL uart_sleep_timer_enabled;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 * rv_general.h is needed for macros Min & Min3.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113 #include "rv/rv_general.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 #include "memif/mem.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 #if ((BOARD == 8) \|\| (BOARD == 9) \|\| (BOARD == 40) \|\| (BOARD == 41))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #include "armio/armio.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 * Maximal value for an unsigned 32 bits.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #define MAX_UNSIGNED_32 (4294967295)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #define FIFO_SIZE (64) /* In bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 * TLR is used to program the RX FIFO trigger levels. FCR[7:4] are not used.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 * No trigger level used for TX FIFO. THR_IT generated on TX FIFO empty.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135 #define RX_FIFO_TRIGGER_LEVEL (12 << 4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 * 16750 addresses. Registers accessed when LCR[7] = 0.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 #define RHR (0x00) /* Rx buffer register - Read access */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 #define THR (0x00) /* Tx holding register - Write access */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #define IER (0x01) /* Interrupt enable register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 * 16750 addresses. Registers accessed when LCR[7] = 1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #define DLL (0x00) /* Divisor latch (LSB) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define DLM (0x01) /* Divisor latch (MSB) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 * EFR is accessed when LCR[7:0] = 0xBF.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define EFR (0x02) /* Enhanced feature register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 * 16750 addresses. Bit 5 of the FCR register is accessed when LCR[7] = 1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define IIR (0x02) /* Interrupt ident. register - Read only */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #define FCR (0x02) /* FIFO control register - Write only */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define LCR (0x03) /* Line control register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define MCR (0x04) /* Modem control register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 #define LSR (0x05) /* Line status register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 #define MSR (0x06) /* Modem status register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define TCR (0x06) /* Transmission control register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #define TLR (0x07) /* Trigger level register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #define MDR1 (0x08) /* Mode definition register 1 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 #define SCR (0x10) /* Supplementary Control register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 #define SSR (0x11) /* Supplementary Status register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define UASR (0x0E) /* Autobauding Status register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 * Supplementary control register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define TX_EMPTY_CTL_IT (0x08)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 #define RX_CTS_WAKE_UP_ENABLE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 #define DSR_IT_BIT (5) /* Use RESET_BIT and SET_BIT macros. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 * Enhanced feature register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 #define ENHANCED_FEATURE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 #define AUTO_CTS_BIT (7) /* Transmission is halted when the CTS pin is high (inactive). */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 * Mode definition register 1.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 #define UART_MODE (0x00)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define SIR_MODE (0x01)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199 #define UART_MODE_AUTOBAUDING (0x02) /* Reserved in UART/IrDA. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #define RESET_DEFAULT_STATE (0x07)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define IR_SLEEP_DISABLED (0x00)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 #define IR_SLEEP_ENABLED (0x08)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 #define SIR_TX_WITHOUT_ACREG2 (0x00) /* Reserved in UART/modem. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 #define SIR_TX_WITH_ACREG2 (0x20) /* Reserved in UART/modem. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 #define FRAME_LENGTH_METHOD (0x00) /* Reserved in UART/modem. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #define EOT_BIT_METHOD (0x80) /* Reserved in UART/modem. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 * Supplementary Status Register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 #define TX_FIFO_FULL (0x01)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 * Interrupt enable register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 #define ERBI (0x01) /* Enable received data available interrupt */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 #define ETBEI (0x02) /* Enable transmitter holding register empty interrupt */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 #define ELSI (0x04) /* Enable receiver line status interrupt */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 #define EDSSI (0x08) /* Enable modem status interrupt */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 #define IER_SLEEP (0x10) /* Enable sleep mode */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 * Modem control register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 #define MDCD (0x01) /* Data Carrier Detect. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 #define MRTS (0x02) /* Request To Send. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 #define TCR_TLR_BIT (6)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 * Line status register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 #define DR (0x01) /* Data ready */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 #define OE (0x02) /* Overrun error */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 #define PE (0x04) /* Parity error */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 #define FE (0x08) /* Framing error */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 #define BI (0x10) /* Break interrupt */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 #define THRE (0x20) /* Transmitter holding register (FIFO empty) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 #define TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 #define BYTE_ERROR (OE \| PE \| FE \| BI)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 * Interrupt identification register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 * Bit 0 is set to 0 if an IT is pending.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 * Bits 1 and 2 are used to identify the IT.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 #define IIR_BITS_USED (0x07)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 #define IT_PENDING (0x01)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 #define RX_DATA (0x04)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 #define TX_EMPTY (0x02)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 #define MODEM_STATUS (0x00)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 * Modem status register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 #define DELTA_CTS (0x01)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 #define DELTA_DSR (0x02)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 #define MCTS (0x10) /* Clear to send */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 #define MDSR (0x20) /* Data set ready */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 * Line control register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 #define WLS_5 (0x00) /* Word length: 5 bits */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 #define WLS_6 (0x01) /* Word length: 6 bits */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #define WLS_7 (0x02) /* Word length: 7 bits */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 #define WLS_8 (0x03) /* Word length: 8 bits */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #define STB (0x04) /* Number of stop bits: 0: 1, 1: 1,5 or 2 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277 #define PEN (0x08) /* Parity enable */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 #define EPS (0x10) /* Even parity select */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 #define BREAK_CONTROL (0x40) /* Enable a break condition */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 #define DLAB (0x80) /* Divisor latch access bit */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 * FIFO control register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 #define FIFO_ENABLE (0x01)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 #define RX_FIFO_RESET (0x02)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define TX_FIFO_RESET (0x04)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 * These constants define the states of the escape sequence detection.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 #define INITIALIZATION (0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 #define NO_ESCAPE_SEQUENCE (1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 #define ONE_CHAR_DETECTED (2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 #define TWO_CHARS_DETECTED (3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 #define THREE_CHARS_DETECTED (4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 #define CHARACTERS_IN_ESC_SEQ (3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 #define DEFAULT_ESC_SEQ_CHARACTER '+'
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define DEFAULT_GUARD_PERIOD (1000) /* 1 second. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 * 3 HISR are used to avoid to execute operations from the LISR.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 #define RX_HISR_PRIORITY (2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 // NGENGE increase hisr stack otherwise overflows with multiple callbacks
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 //#define RX_HISR_STACK_SIZE (512) /* Bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 #define RX_HISR_STACK_SIZE (768) /* Bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 #define TX_HISR_PRIORITY (2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 // NGENGE increase hisr stack otherwise overflows with multiple callbacks
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 //#define TX_HISR_STACK_SIZE (512) /* Bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 #define TX_HISR_STACK_SIZE (768) /* Bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 #define V24_HISR_PRIORITY (2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 #define V24_HISR_STACK_SIZE (512) /* Bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 * When the break interrupt indicator (BI) is set in the line status register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 * (LSR), it indicates that the received data input was held in the low state
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 * for longer than a full-word transmission time. In the FIFO mode, when a break
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 * occurs, only one 0 character is loaded into the FIFO. The next character
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 * transfer is enabled after SIN goes to the marking state for at least two RCLK
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 * samples and then receives the next valid start bit.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 * This constant defined a defined break length returned by the US_GetLineState
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 * function.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 #define MINIMAL_BREAK_LENGTH (2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 #define BREAK_HISR_PRIORITY (2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 #define BREAK_HISR_STACK_SIZE (512) /* Bytes. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 * These macros allow to read and write a UART register.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 #define READ_UART_REGISTER(UART,REG) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 ((volatile SYS_UWORD8 ) ((UART)->base_address + (REG)))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 #define WRITE_UART_REGISTER(UART,REG,VALUE) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 ((volatile SYS_UWORD8 ) ((UART)->base_address + (REG))) = (VALUE)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #define RESET_BIT(UART,REG,BIT) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 (WRITE_UART_REGISTER ( \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT))))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 #define SET_BIT(UART,REG,BIT) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 (WRITE_UART_REGISTER ( \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 UART, REG, READ_UART_REGISTER (UART, REG) \| (1 << (BIT))))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 * These macros allow to enable or disable the wake-up interrupt.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 #define ENABLE_WAKEUP_INTERRUPT(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 SET_BIT(UART, SCR, RX_CTS_WAKE_UP_ENABLE_BIT);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 #define DISABLE_WAKEUP_INTERRUPT(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 RESET_BIT(UART, SCR, RX_CTS_WAKE_UP_ENABLE_BIT);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 * These macros allow to enable or disable the DSR interrupt.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384 #define ENABLE_DSR_INTERRUPT(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 SET_BIT(UART, SCR, DSR_IT_BIT);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 #define DISABLE_DSR_INTERRUPT(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 RESET_BIT(UART, SCR, DSR_IT_BIT);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 * The transmitter is disabled only when the application disables the driver.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 * To disable the driver, the receiver and the transmitter are disabled by the
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 * application. The transmitter is disabled first to test if the driver is
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 * disabled.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 #define DRIVER_DISABLED(UART) ((UART)->tx_stopped_by_application)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 #define DISABLE_DRIVER(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 { \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 (UART)->tx_stopped_by_application = 1; \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 (UART)->rx_stopped_by_application = 1; \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #define ENABLE_DRIVER(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 { \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 (UART)->rx_stopped_by_application = 0; \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 (UART)->tx_stopped_by_application = 0; \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 * Low and high watermarks for the RX buffer. If it is enabled, the flow
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 * control is activated or deactivated according to these values.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 * The high watermark value allows to copy an array filled with the RX FIFO
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 * into the RX buffer.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419 #define RX_LOW_WATERMARK(RX_BUFFER_SIZE) (FIFO_SIZE)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #define RX_HIGH_WATERMARK(RX_BUFFER_SIZE) ((RX_BUFFER_SIZE) - 2 * FIFO_SIZE)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 * This macro allows to know if the RX buffer is full. It must be called only
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 * from the RX HISR. If it is called from the application, the rx_in and
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 * rx_fifo_in pointers may be updated if a RX interrupt occurs or if the
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 * RX HISR is activated.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 #define RX_BUFFER_FULL(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 (((UART)->rx_in == (UART)->rx_out - 1) \|\| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 ((UART)->rx_in == (UART)->rx_out + (UART)->buffer_size))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 * This macro allows to know if the TX buffer is empty.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 #define TX_BUFFER_EMPTY(UART) \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 ((UART)->tx_in == (UART)->tx_out)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 * This macro is used to convert a time (unit: ms) into a number of TDMA.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 * 1 TDMA = 4.6 ms (23/5).
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 #define CONVERT_TIME_IN_TDMA(TIME) (((TIME) * 5) / 23)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 * This structure describes an UART compatible with the UART 16750 and
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 * contains some fields to manage this UART.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 typedef struct s_uart {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 SYS_UWORD32 base_address;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 * HISR executed from the RX/TX interrupt handler.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 NU_HISR rx_hisr_ctrl_block;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 NU_HISR tx_hisr_ctrl_block;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 NU_HISR v24_hisr_ctrl_block;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 char rx_hisr_stack[RX_HISR_STACK_SIZE];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 char tx_hisr_stack[TX_HISR_STACK_SIZE];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 char v24_hisr_stack[V24_HISR_STACK_SIZE];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469 * 2 arrays are used to store bytes read in RX FIFO. A UART RX interrupt
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 * may occur while executing RX operations in RX HISR. To avoid overwriting
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 * the array in which received bytes are stored, a second array is used.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 SYS_UWORD8 *rx_buffer_used_by_rx_lisr;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 SYS_UWORD8 *rx_buffer_used_by_rx_hisr;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 SYS_UWORD8 rx_fifo_byte_1[FIFO_SIZE];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 SYS_UWORD8 rx_fifo_byte_2[FIFO_SIZE];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 SYS_UWORD16 bytes_in_rx_buffer_1;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 SYS_UWORD16 bytes_in_rx_buffer_2;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 * RX and TX buffers.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 * One character is not used in each buffer to allow to know if the buffer
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 * is empty or not (See macro RX_BUFFER_FULL). If buffers are empty,
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 * rx_in = rx_out and tx_in = tx_out. It is impossible to use fields to
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 * count the number of bytes in each buffer because these fields may be
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 * updated from the application and from the interrupt handlers. That avoids
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 * to have conflicts.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 SYS_UWORD16 buffer_size;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 SYS_UWORD16 rx_threshold_level;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 SYS_UWORD16 tx_threshold_level;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 SYS_UWORD8 rx_buffer[FD_MAX_BUFFER_SIZE + 1];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 SYS_UWORD8 tx_buffer[FD_MAX_BUFFER_SIZE + 1];
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 SYS_UWORD8 *rx_in;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 SYS_UWORD8 *rx_out;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 SYS_UWORD8 *tx_in;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 SYS_UWORD8 *tx_out;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500

0

b6a5e36de839 src/cs: initial import from Magnetite