fc-selenite: src/cs/layer1/tpu_drivers/source/tpudrv.c annotate

annotate src/cs/layer1/tpu_drivers/source/tpudrv.c @ 47:d2074d1102e0

L1 data section placement: support both TMS470 and gcc

author	Mychaela Falconia <falcon@freecalypso.org>
date	Thu, 19 Jul 2018 01:04:05 +0000
parents	b6a5e36de839
children

rev	line source
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*********** Revision Controle System Header ***********
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 * Filename tpudrv.c
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Copyright 2003 (C) Texas Instruments
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *********** Revision Controle System Header ***********/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 * TPUDRV.C
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 * TPU driver for Pole Star
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 * Copyright (c) Texas Instruments 1996
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "l1_macro.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 #include "iq.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 #include "l1_confg.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 #include "l1_const.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 #include "l1_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #if (AUDIO_TASK == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 #include "l1audio_const.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 #include "l1audio_cust.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 #include "l1audio_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #if (L1_GTT == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #include "l1gtt_const.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #include "l1gtt_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #if (L1_MIDI == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #include "l1midi_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 #include "sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 #if TESTMODE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #include "l1tm_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #if (L1_MP3 == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #include "l1mp3_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #if (L1_MIDI == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #include "l1midi_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #if (L1_AAC == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #include "l1aac_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56 #include "l1_defty.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 #include "tpudrv.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #include "sys_types.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #include "clkm.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #include "l1_time.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #include "l1_varex.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #include "l1_trace.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #if (L1_MADC_ON == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #if (RF_FAM == 61)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #include "drp_api.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #include "l1_rf61.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #include "drp_drive.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #include "tpudrv61.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 extern T_DRP_REGS_STR *drp_regs;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #endif //L1_MADC_ON
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 /* RFTime environment */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #if defined (HOST_TEST)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #include "hostmacros.h"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 * VEGA and OMEGA receive windows - Defined in Customer-specific file
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 extern UWORD32 debug_tpu;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 // WCS Patch : ADC during RX or TX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 * Global Variables
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94 // GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 //------------------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 SYS_UWORD16 TP_Ptr = (SYS_UWORD16 ) TPU_RAM;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 /* TPU_Reset : Reset the TPU */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 /* Parameters : on/off(1/0) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 /* Functionality : ) Reset the TPU */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 void TPU_Reset(SYS_UWORD16 on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 if (on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 * ((volatile SYS_UWORD16 *) TPU_CTRL) \|= TPU_CTRL_RESET;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 while (!(((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_RESET));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 while ((((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_RESET));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 /* TSP_Reset : Reset the TSP */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 /* Parameters : on/off(1/0) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 /* Functionality : ) Reset the TSP */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 void TSP_Reset(SYS_UWORD16 on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 if (on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 * ((volatile SYS_UWORD16 *) TPU_CTRL) \|= TSP_CTRL_RESET;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135 while (!(((volatile SYS_UWORD16 ) TPU_CTRL) & TSP_CTRL_RESET));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 while ((((volatile SYS_UWORD16 ) TPU_CTRL) & TSP_CTRL_RESET));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 /* TPU_SPIReset : Reset the SPI of the TPU */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 /* Parameters : on/off(1/0) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 /* Functionality : ) the SPI of the TPU */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 void TPU_SPIReset(SYS_UWORD16 on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 if (on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 * ((volatile SYS_UWORD16 *) TPU_CTRL) \|= TPU_CTRL_SPI_RST;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 while (!(((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_SPI_RST));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 while ((((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_SPI_RST));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 /* TPU_ClkEnable : */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 /* Parameters : on/off(1/0) */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 /* Functionality : Enable the TPU clock */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 void TPU_ClkEnable(SYS_UWORD16 on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 if (on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 * ((volatile SYS_UWORD16 *) TPU_CTRL) \|= TPU_CTRL_CLK_EN;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 while (!(((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_CLK_EN));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 while ((((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_CLK_EN));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 /* TPU_Frame_ItOn : */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196 /* Parameters : bit of it to enable */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 /* Functionality : Enable frame it */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 /-----------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 /* Warning read modify write access to TPU_INT_CTRL register */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 /* may generate problems using Hyperion. */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 /-----------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 void TPU_FrameItOn(SYS_UWORD16 it)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 void TPU_FrameItEnable(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #if W_A_ITFORCE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214 ((volatile SYS_UWORD16 )TPU_INT_CTRL) \|= TPU_INT_ITD_F;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 // enable IT_DSP generation on next frame
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 // reset by DSP when IT occurs
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 ((volatile SYS_UWORD16 ) TPU_CTRL) \|= TPU_CTRL_D_ENBL;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 while (!(((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_D_ENBL));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 /* TPU_check_IT_DSP : */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 /* Parameters : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 /* Functionality : check if an IT DSP still pending */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 BOOL TPU_check_IT_DSP(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 { // return TRUE if an IT DSP still pending.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 return( ((((volatile SYS_UWORD16 ) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 /* TPU_DisableAllIt : */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 /* Parameters : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 /* Return : none */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 /* Functionality : Disabl all it */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 /--------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 void TPU_DisableAllIt()
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) \|= TPU_INT_ITF_M \| TPU_INT_ITP_M \| TPU_INT_ITD_M;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 * TP_Program
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 * Write a null-terminated scenario into TPU memory at a given start address
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 * (Do not write terminating 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 void TP_Program(const SYS_UWORD16 *src)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 /* Write TPU instructions until SLEEP */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 while (*src)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 TP_Ptr++ = src++;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 void TP_Reset(SYS_UWORD16 on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 if (on) {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 * ((volatile SYS_UWORD16 *) TPU_CTRL) \|= (TPU_CTRL_RESET \| TSP_CTRL_RESET);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 while (!(((volatile SYS_UWORD16 ) TPU_CTRL) & (TPU_CTRL_RESET \| TSP_CTRL_RESET)));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 else {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET \| TSP_CTRL_RESET);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 while ((((volatile SYS_UWORD16 ) TPU_CTRL) & (TPU_CTRL_RESET \| TSP_CTRL_RESET)));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 void TP_Enable(SYS_UWORD16 on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 if(on)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 * ((volatile SYS_UWORD16 *) TPU_CTRL) \|= TPU_CTRL_T_ENBL;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 // Some time shall be wait before leaving the function to ensure that bit has been taken
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292 else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 // Some time shall be wait before leaving the function to ensure that bit has been taken
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 #if 0 /* FreeCalypso: function not present in TCS211 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 /* Function name: TPU_wait_idle */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 /* Parameters: None */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 /* Return: None */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 /* Description: Wait until TPU scenario execution is complete */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 /* */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 /-----------------------------------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 void TPU_wait_idle(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 while( (((volatile SYS_UWORD16 ) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 wait_ARM_cycles(convert_nanosec_to_cycles(3000));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 * l1dmacro_idle
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 * Write SLEEP instruction, start TPU and reset pointer
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 void l1dmacro_idle (void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 *TP_Ptr++ = TPU_SLEEP;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 /* start TPU */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 TP_Enable(1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 * l1dmacro_offset
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 * Set OFFSET register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 // WARNING: 'relative time' and 'offset_value' must always be comprised
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 // between 0 and TPU_CLOCK_RANGE !!!
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 if (relative_time != IMM) // IMM indicates to set directly without AT
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 *TP_Ptr++ = TPU_FAT(relative_time);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 *TP_Ptr++ = TPU_OFFSET(offset_value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 * l1dmacro_synchro
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 * Set synchro register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 void l1dmacro_synchro (UWORD32 when, UWORD32 value)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!!
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 trace_fct(CST_L1DMACRO_SYNCHRO, -1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 if (value != IMM) // IMM indicates to set directly without AT
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 *TP_Ptr++ = TPU_FAT(when);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 *TP_Ptr++ = TPU_SYNC(value);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 l1s.tpu_offset_hw = value; // memorize the offset set into the TPU.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 * l1dmacro_adc_read
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 void l1dmacro_adc_read_rx(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 // TSP needs to be configured in order to send serially to Omega
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 // *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 *TP_Ptr++ = TPU_WAIT (5);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 *TP_Ptr++ = TPU_WAIT (5);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 #if (TRACE_TYPE==1)\|\|(TRACE_TYPE ==4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 #if (GSM_IDLE_RAM == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 l1_trace_ADC(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 l1_trace_ADC_intram(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 #if (L1_MADC_ON == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 #if (ANLG_FAM == 11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 #if (TRACE_TYPE==1)\|\|(TRACE_TYPE ==4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 #if (GSM_IDLE_RAM == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 l1_trace_ADC(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417 l1_trace_ADC_intram(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 // WCS patch: ADC during RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 GC_SetAdcInfo(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 #if (CODE_VERSION != SIMULATION)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 #if (L1_MADC_ON ==1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 * l1dmacro_adc_read_rx_cs_mode0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 * Purpose:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 * ======
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 * increases and can be as high as 360 seconds (Maximum Value)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 * This can result in battery related issues like phone powering off without MMI indication.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 void l1dmacro_adc_read_rx_cs_mode0(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 *TP_Ptr++ = TPU_WAIT (2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 #if (L1_MADC_ON == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 #if (ANLG_FAM == 11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 #if (TRACE_TYPE==1)\|\|(TRACE_TYPE ==4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 #if (GSM_IDLE_RAM == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 l1_trace_ADC(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 l1_trace_ADC_intram(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 // WCS patch: ADC during RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 GC_SetAdcInfo(0);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 #endif //If MADC is enabled
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 #endif //If Not Simulation
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 * l1dmacro_adc_read_tx
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 #if (ANLG_FAM != 11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 void l1dmacro_adc_read_tx(UWORD32 when)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 *TP_Ptr++ = TPU_FAT (when);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC\|BULON\|BULENA); // Load data to send
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 *TP_Ptr++ = TPU_WAIT (5);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON\|BULENA);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 #if (TRACE_TYPE==1)\|\|(TRACE_TYPE ==4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 l1_trace_ADC(1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 #if (L1_MADC_ON == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 #if (ANLG_FAM == 11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 *TP_Ptr++ = TPU_FAT (when);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state \| START_ADC);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 *TP_Ptr++ = TPU_WAIT (2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 #if 1 // TEMP MEASUREMENT - uncomment and test after MADC
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 #if (RF_FAM == 61)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 //TEMP_MEAS: Call TEMP Conv Script in DRP
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL));
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #if (TRACE_TYPE==1)\|\|(TRACE_TYPE ==4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 l1_trace_ADC(1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 #endif //L1_MADC_ON
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 // WCS patch: ADC during TX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 GC_SetAdcInfo(1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539 #if (RF_FAM == 61)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 int i;
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 *TP_Ptr++ = TPU_FAT (when);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state \| START_ADC);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 *TP_Ptr++ = TPU_WAIT (2);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #if (TRACE_TYPE==1)\|\|(TRACE_TYPE ==4)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 l1_trace_ADC(1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 // WCS patch: ADC during TX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 GC_SetAdcInfo(1);
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 }
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 /*
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 * l1dmacro_set_frame_it
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567 */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 void l1dmacro_set_frame_it(void)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 {
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 TPU_FrameItEnable();
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 }

FreeCalypso > hg > fc-selenite

annotate src/cs/layer1/tpu_drivers/source/tpudrv.c @ 47:d2074d1102e0