FreeCalypso > hg > fc-selenite
annotate src/cs/layer1/tpu_drivers/source0/tpudrv2.h @ 153:df9c471ce9e9
l1_rf12.c and tpudrv12.[ch]: updates from Magnetite
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 10 Mar 2019 20:28:06 +0000 |
parents | b6a5e36de839 |
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rev | line source |
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1 /****************** Revision Controle System Header *********************** |
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2 * GSM Layer 1 software |
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3 * Copyright (c) Texas Instruments 1998 |
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4 * |
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5 * Filename tpudrv2.h |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ****************** Revision Controle System Header ***********************/ |
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9 |
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10 /***********************************************************/ |
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11 /* */ |
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12 /* Used Timing definitions given in "L1_TIME.H" */ |
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13 /* -------------------------------------------- */ |
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14 /* */ |
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15 /* START_RX_FB STOP_RX_FB */ |
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16 /* START_RX_SB STOP_RX_SB */ |
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17 /* START_RX_SNB STOP_RX_SNB */ |
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18 /* START_RX_NNB STOP_RX_NNB */ |
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19 /* START_RX_PW_1 STOP_RX_PW_1 */ |
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20 /* START_RX_FB26 STOP_RX_FB26 */ |
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21 /* START_TX_NB STOP_TX_NB */ |
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22 /* START_RX_RA STOP_RX_RA */ |
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23 /* */ |
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24 /***********************************************************/ |
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25 |
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26 // BB Timings |
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27 #define VG_CAL_RX_DELAY 65 |
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28 #define VG_CAL_TX_DELAY 143 |
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29 #define VG_BDLON_DELAY 70 |
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30 #define VG_BULOFF_DELAY 35 |
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31 #define VG_BULON_DELAY 159 |
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32 |
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33 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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34 #define OM_CAL_RX_DELAY 65 |
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35 #define OM_CAL_TX_DELAY 230 |
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36 #define OM_BDLON_DELAY 166 |
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37 #define OM_BULOFF_DELAY 35 |
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38 #define OM_BULON_DELAY 250 |
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39 |
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40 #define SL_SU_DELAY1 4 |
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41 #define SL_SU_DELAY2 3 |
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42 #endif |
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43 |
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44 #define RA_TRANSMIS_DURATION ( RA_BURST_DURATION + 46L ) |
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45 #define NB_TRANSMIS_DURATION ( NB_BURST_DURATION_UL + 29L ) |
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46 #define START_TX_NB ( 4984L ) // Calibration time is reduced of 4 GSM bit due to a slow APC ramp |
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47 #define STOP_TX_NB ( START_TX_NB + NB_TRANSMIS_DURATION ) |
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48 #define STOP_TX_RA ( START_TX_RA + RA_TRANSMIS_DURATION ) |
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49 |
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50 |
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51 #ifdef TPUDRV2_C |
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52 |
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53 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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54 const unsigned short RF_Sleep[] ={ |
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55 /*** Immediate ***/ |
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56 TPU_MOVE(TSP_SPI_SET1, TSP_ENA_POS_MSB), |
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57 TPU_MOVE(TSP_SPI_SET2, TSP_ENA_POS_MSB | TSP_ENA_POS), |
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58 0 |
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59 }; |
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60 |
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61 const unsigned short RF_Wakeup[] ={ |
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62 /*** Immediate ***/ |
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63 TPU_MOVE(TSP_SPI_SET1, 0x00), |
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64 TPU_MOVE(TSP_SPI_SET2, TSP_ENA_POS), |
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65 0 |
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66 }; |
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67 |
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68 |
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69 /*--------------------------------------------------------------------------------------------------------------*/ |
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70 /* Serial link delay for OMEGA. this delay includes */ |
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71 /* TSP register programming and serialization of data to OMEGA */ |
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72 /* */ |
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73 /* */ |
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74 /* 4991 4992 4993 4994 4995 4996 4997 */ |
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75 /* ---------------------------------------------------------------------------------------------- */ |
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76 /* | | | | | | | */ |
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77 /*OMEGA | AT(4991) | Clock conf | Nb of bit | Load data | Send write | Serialization */ |
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78 /* | | | to shift | to shift | command | | */ |
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79 /* ---------------------------------------------------------------------------------------------- */ |
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80 /* | | | | | | | */ |
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81 /* VEGA | | | | | | AT(4996) | TSPACT */ |
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82 /* | | | | | | | */ |
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83 /* ------------------------------------------------------------------------------------------|--- */ |
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84 /* <------------------------------------------------------------------> | */ |
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85 /* SL_SU_DELAY1 | */ |
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86 /* V */ |
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87 /* ACTION ON WINDOW */ |
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88 /* */ |
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89 /* When the TSP port is already configured is not necessary to configure the clock and the number of bits */ |
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90 /* */ |
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91 /* */ |
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92 /* 4998 4999 0 1 2 */ |
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93 /* ------------------------------------------------------------------- */ |
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94 /* | | | | | | */ |
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95 /*OMEGA | AT(4998) | Load data | Send write | Serialization | */ |
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96 /* | | to shift | command | | | */ |
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97 /* ---------------------------------------------------------------------- */ |
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98 /* | | | | | | */ |
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99 /* VEGA | | | | AT(4996) | TSPACT */ |
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100 /* | | | | | | */ |
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101 /* ------------------------------------------------------------|------- */ |
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102 /* <---------------------------------------> | */ |
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103 /* SL_SU_DELAY2 | */ |
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104 /* V */ |
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105 /* ACTION ON WINDOW */ |
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106 /* */ |
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107 /* */ |
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108 /* NOTE : WITH THIS IMPLEMENTATION THE OMEGA SCENARIO ANTICIPATES THE ACTION ON WINDOW SIGNAL OF 347 ns. */ |
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109 /* ANYWAY ACTION IS TAKEN IN THE SAME QB INTERVAL */ |
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110 /* */ |
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111 /* */ |
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112 /*--------------------------------------------------------------------------------------------------------------*/ |
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113 |
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114 |
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115 |
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116 /***********************************************************/ |
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117 /* BASEBAND TPU SCENARIOS FOR OMEGA */ |
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118 /***********************************************************/ |
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119 |
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120 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) |
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121 // Samson TPU scenario: add 1 bit to reception window for DMA thres = 2 |
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122 const SYS_UWORD16 VG_DlNormalBurst [] = { |
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123 |
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124 TPU_AT (START_RX_SNB -VG_BDLON_DELAY - SL_SU_DELAY1 ), // AT(4991) |
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125 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), |
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126 TPU_MOVE (TSP_CTRL1,6), |
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127 TPU_MOVE (TSP_TX_REG_1,BDLON), |
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128 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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129 |
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130 |
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131 TPU_AT (START_RX_SNB - VG_CAL_RX_DELAY - SL_SU_DELAY2), // AT(4998) |
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132 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), |
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133 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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134 |
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135 TPU_AT (START_RX_SNB - SL_SU_DELAY2), // AT(63) |
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136 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), |
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137 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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138 |
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139 TPU_AT (STOP_RX_SNB - SL_SU_DELAY2), // AT(699) |
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140 TPU_MOVE (TSP_TX_REG_1,0x00), |
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141 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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142 |
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143 0 |
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144 }; |
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145 |
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146 |
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147 // HERCULES TPU scenario |
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148 const SYS_UWORD16 VG_DlFrequencyBurstIdle [] = { |
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149 |
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150 TPU_AT (START_RX_FB - VG_BDLON_DELAY -SL_SU_DELAY1 ), // AT(4991) |
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151 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), |
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152 TPU_MOVE (TSP_CTRL1,6), |
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153 TPU_MOVE (TSP_TX_REG_1,BDLON), |
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154 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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155 |
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156 |
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157 TPU_AT (START_RX_FB - VG_CAL_RX_DELAY -SL_SU_DELAY2), // AT(4998) |
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158 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), |
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159 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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160 |
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161 |
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162 TPU_AT (START_RX_FB - SL_SU_DELAY2), // AT(63) |
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163 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), |
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164 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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165 |
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166 TPU_AT (0), |
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167 TPU_AT (0), |
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168 TPU_AT (0), |
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169 TPU_AT (0), |
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170 TPU_AT (0), |
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171 TPU_AT (0), |
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172 TPU_AT (0), |
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173 TPU_AT (0), |
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174 TPU_AT (0), |
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175 TPU_AT (0), |
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176 TPU_AT (0), |
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177 |
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178 TPU_AT (STOP_RX_FB - SL_SU_DELAY2), // AT(2119) |
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179 TPU_MOVE (TSP_TX_REG_1,0X00), |
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180 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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181 |
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182 0 |
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183 }; |
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184 |
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185 |
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186 #else |
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187 /* HERCULES TPU scenario */ |
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188 |
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189 const SYS_UWORD16 VG_DlNormalBurst [] = { |
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190 |
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191 TPU_AT (START_RX_SNB -VG_BDLON_DELAY - SL_SU_DELAY1 ), // AT(4991) |
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192 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), |
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193 TPU_MOVE (TSP_CTRL1,6), |
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194 TPU_MOVE (TSP_TX_REG_1,BDLON), |
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195 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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196 |
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197 |
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198 TPU_AT (START_RX_SNB - VG_CAL_RX_DELAY - SL_SU_DELAY2), // AT(4998) |
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199 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), |
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200 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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201 |
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202 TPU_AT (START_RX_SNB - SL_SU_DELAY2), // AT(63) |
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203 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), |
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204 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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205 |
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206 TPU_AT (STOP_RX_SNB - SL_SU_DELAY2), // AT(699) |
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207 TPU_MOVE (TSP_TX_REG_1,0x00), |
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208 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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209 |
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210 0 |
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211 }; |
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212 |
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213 |
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214 // HERCULES TPU scenario |
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215 const SYS_UWORD16 VG_DlFrequencyBurstIdle [] = { |
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216 |
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217 TPU_AT (START_RX_FB - VG_BDLON_DELAY -SL_SU_DELAY1 ), // AT(4991) |
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218 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), |
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219 TPU_MOVE (TSP_CTRL1,6), |
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220 TPU_MOVE (TSP_TX_REG_1,BDLON), |
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221 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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222 |
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223 |
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224 TPU_AT (START_RX_FB - VG_CAL_RX_DELAY -SL_SU_DELAY2), // AT(4998) |
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225 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), |
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226 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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227 |
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228 |
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229 TPU_AT (START_RX_FB - SL_SU_DELAY2), // AT(63) |
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230 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), |
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231 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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232 |
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233 TPU_AT (0), |
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234 TPU_AT (0), |
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235 TPU_AT (0), |
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236 TPU_AT (0), |
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237 TPU_AT (0), |
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238 TPU_AT (0), |
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239 TPU_AT (0), |
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240 TPU_AT (0), |
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241 TPU_AT (0), |
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242 TPU_AT (0), |
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243 TPU_AT (0), |
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244 |
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245 TPU_AT (STOP_RX_FB - SL_SU_DELAY2), // AT(2119) |
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246 TPU_MOVE (TSP_TX_REG_1,0X00), |
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247 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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248 |
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249 0 |
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250 }; |
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251 |
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252 |
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253 |
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254 #endif |
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255 |
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256 |
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257 |
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258 // HERCULES TPU scenario for Omega windows reset |
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259 const SYS_UWORD16 VG_Omega_win_reset[] = { |
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260 |
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261 TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), |
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262 TPU_MOVE (TSP_CTRL1,6), |
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263 TPU_MOVE (TSP_TX_REG_1,0x00), |
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264 TPU_MOVE (TSP_CTRL2, TC2_WR), |
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265 0 |
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266 }; |
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267 |
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268 #endif |
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269 |
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270 #else |
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271 extern const SYS_UWORD16 VG_DlNormalBurst[]; |
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272 extern const SYS_UWORD16 VG_DlFrequencyBurstIdle[]; |
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273 #endif |
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274 |