FreeCalypso > hg > fc-selenite
annotate src/cs/drivers/drv_app/ffs/board/amdsbdrv.c @ 157:fd5202e290bc
targets: j100 added
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 17 Mar 2019 07:13:14 +0000 |
parents | 4484ab3f6ab3 |
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rev | line source |
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1 /****************************************************************************** |
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2 * Flash File System (ffs) |
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com |
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4 * |
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5 * FFS AMD single bank low level flash driver RAM code |
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6 * |
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7 * $Id: amdsbdrv.c 1.5.1.3 Tue, 06 Jan 2004 10:57:45 +0100 tsj $ |
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8 * |
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9 ******************************************************************************/ |
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10 |
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11 #include "ffs.cfg" |
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12 |
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13 #include "ffs/ffs.h" |
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14 #include "ffs/board/drv.h" |
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15 #include "ffs/board/ffstrace.h" |
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16 |
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17 |
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18 // Due to long branches, we disable all tracing and led function calls. |
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19 #undef tlw |
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20 #define tlw(contents) |
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21 #undef ttw |
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22 #define ttw(contents) |
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23 |
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24 |
46
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25 #ifdef __GNUC__ |
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26 asm(".globl ffsdrv_ram_amd_begin"); |
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27 asm("ffsdrv_ram_amd_begin:"); |
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28 #else |
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29 asm(" .label _ffsdrv_ram_amd_begin"); |
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30 asm(" .def _ffsdrv_ram_amd_begin"); |
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31 #endif |
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32 |
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33 |
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34 // IMPORTANT! Apparently, placing the int_disable/enable() function code |
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35 // here instead of at the bottom of the file, makes the code crash or |
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36 // freeze. Reason is as of yet unknown. |
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37 |
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38 uint32 amd_int_disable(void); |
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39 void amd_int_enable(uint32 tmp); |
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40 |
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41 |
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42 /****************************************************************************** |
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43 * AMD Single Bank Driver Functions |
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44 ******************************************************************************/ |
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45 |
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46 void ffsdrv_ram_amd_sb_write_halfword(volatile uint16 *addr, uint16 value) |
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47 { |
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48 volatile char *flash = dev.base; |
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49 uint32 cpsr; |
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50 |
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51 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value)); |
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52 |
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53 if (~*addr & value) { |
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54 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value)); |
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55 return; |
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56 } |
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57 |
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58 cpsr = amd_int_disable(); |
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59 tlw(led_on(LED_WRITE)); |
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60 |
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61 flash[0xAAAA] = 0xAA; // AMD unlock cycle 1 |
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62 flash[0x5555] = 0x55; // AMD unlock cycle 2 |
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63 flash[0xAAAA] = 0xA0; |
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64 *addr = value; |
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65 |
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66 while ((*addr ^ value) & 0x80) |
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67 ; |
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68 |
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69 tlw(led_off(LED_WRITE)); |
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70 amd_int_enable(cpsr); |
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71 } |
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72 |
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73 // This VERY simple way of erase suspension only works because we run under |
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74 // a pre-emptive operating system, so whenever an interrupt occurs, another |
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75 // task takes the CPU, and at the end of the interrupt, FFS gets the CPU |
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76 // again. |
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77 void ffsdrv_ram_amd_sb_erase(uint8 block) |
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78 { |
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79 volatile char *flash = dev.base; |
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80 volatile char *addr; |
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81 uint32 cpsr; |
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82 uint16 flashpoll; |
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83 |
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84 addr = block2addr(block); |
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85 |
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86 ttw(ttr(TTrDrvEra, "e(%d)" NL, block)); |
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87 |
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88 cpsr = amd_int_disable(); |
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89 tlw(led_on(LED_ERASE)); |
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90 |
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91 flash[0xAAAA] = 0xAA; // AMD unlock cycle 1 |
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92 flash[0x5555] = 0x55; // AMD unlock cycle 2 |
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93 flash[0xAAAA] = 0x80; |
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94 flash[0xAAAA] = 0xAA; // AMD unlock cycle 1 |
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95 flash[0x5555] = 0x55; // AMD unlock cycle 2 |
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96 *addr = 0x30; // AMD erase sector command |
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97 |
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98 // Wait for erase to finish. |
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99 while ((*addr & 0x80) == 0) { |
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100 tlw(led_toggle(LED_ERASE)); |
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101 // Poll interrupts, taking interrupt mask into account. |
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102 if (INT_REQUESTED) |
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103 { |
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104 // 1. suspend erase |
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105 // 2. enable interrupts |
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106 // .. now the interrupt code executes |
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107 // 3. disable interrupts |
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108 // 4. resume erase |
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109 |
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110 tlw(led_on(LED_ERASE_SUSPEND)); |
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111 *addr = 0xB0; |
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112 |
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113 // wait for erase suspend to finish |
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114 while ((*addr & 0x80) == 0) |
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115 ; |
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116 |
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117 tlw(led_off(LED_ERASE_SUSPEND)); |
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118 amd_int_enable(cpsr); |
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119 |
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120 // Other interrupts and tasks run now... |
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121 |
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122 cpsr = amd_int_disable(); |
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123 tlw(led_on(LED_ERASE_SUSPEND)); |
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124 |
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125 // Before resuming erase we must? check if the erase is really |
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126 // suspended or if it did finish |
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127 flashpoll = *addr; |
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128 *addr = 0x30; |
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129 |
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130 tlw(led_off(LED_ERASE_SUSPEND)); |
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131 } |
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132 } |
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133 |
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134 tlw(led_on(LED_ERASE)); |
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135 tlw(led_off(LED_ERASE)); |
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136 amd_int_enable(cpsr); |
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137 } |
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138 |
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139 |
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140 /****************************************************************************** |
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141 * Interrupt Enable/Disable |
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142 ******************************************************************************/ |
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143 |
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144 #ifdef __GNUC__ |
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145 #define NOINLINE __attribute__ ((noinline)) |
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146 #else |
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147 #define NOINLINE |
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148 #endif |
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149 |
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150 uint32 NOINLINE amd_int_disable(void) |
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151 { |
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152 #ifdef __GNUC__ |
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153 asm(" .code 16"); |
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154 #else |
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155 asm(" .state16"); |
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156 #endif |
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157 asm(" mov A1, #0xC0"); |
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158 asm(" ldr A2, tct_amd_disable"); |
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159 asm(" bx A2 "); |
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160 |
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161 #ifdef __GNUC__ |
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162 asm(".balign 4"); |
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163 asm("tct_amd_disable:"); |
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164 asm(" .word TCT_Control_Interrupts"); |
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165 #else |
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166 asm("tct_amd_disable .field _TCT_Control_Interrupts+0,32"); |
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167 asm(" .global _TCT_Control_Interrupts"); |
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168 #endif |
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169 } |
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170 |
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171 void NOINLINE amd_int_enable(uint32 cpsr) |
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172 { |
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173 #ifdef __GNUC__ |
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174 asm(" .code 16"); |
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175 #else |
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176 asm(" .state16"); |
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177 #endif |
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178 asm(" ldr A2, tct_amd_enable"); |
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179 asm(" bx A2 "); |
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180 |
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181 #ifdef __GNUC__ |
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182 asm(".balign 4"); |
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183 asm("tct_amd_enable:"); |
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184 asm(" .word TCT_Control_Interrupts"); |
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185 #else |
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186 asm("tct_amd_enable .field _TCT_Control_Interrupts+0,32"); |
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187 asm(" .global _TCT_Control_Interrupts"); |
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188 #endif |
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189 } |
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190 |
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191 // Even though we have this end label, we cannot determine the number of |
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192 // constant/PC-relative data following the code! |
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193 #ifdef __GNUC__ |
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194 asm(".globl ffsdrv_ram_amd_end"); |
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195 asm("ffsdrv_ram_amd_end:"); |
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196 #else |
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197 asm(" .state32"); |
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198 asm(" .label _ffsdrv_ram_amd_end"); |
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199 asm(" .def _ffsdrv_ram_amd_end"); |
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200 #endif |