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l1_init.c: sync with Tourmaline: L1 recovery ABB init fix
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 31 Oct 2022 01:23:14 +0000
parents b6a5e36de839
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*
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2 * Integrated Protocol Stack Linker command file (all components)
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3 *
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4 * Target : ARM
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5 *
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6 * Copyright (c) Texas Instruments 2002, Condat 2002
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7 *
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8 */
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9
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10 -c /* Autoinitialize variables at runtime */
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11
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12 /*********************************/
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13 /* SPECIFY THE SYSTEM MEMORY MAP */
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14 /*********************************/
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15
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16 MEMORY
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17 {
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18 /* CS0: Flash 8 Mbytes ****************************************************/
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19 /* Interrupt Vectors Table */
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20 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
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21
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22 /* Boot Sector */
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23 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
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24
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25 /* Magic Word for Calypso Boot ROM */
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26 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
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27
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28 /* Program Memory */
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29 P_MEM1 (RXI) : org = 0x00010000 len = 0x00000700
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30 P_MEM2 (RXI) : org = 0x00010700 len = 0x00000004
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31 P_MEM3 (RXI) : org = 0x00010704 len = 0x00400000
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32 P_MEM4 (RXI) : org = 0x00410704 len = 0x002ef8fc
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33
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34 /* FFS Area */
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35 FFS_MEM (RX) : org = 0x01800000 len = 0x00200000
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36 /**************************************************************************/
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37
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38 /* CS1: External SRAM 1 Mbytes ********************************************/
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39 /* Data Memory */
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40 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
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41 /**************************************************************************/
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42
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43 /* CS2: External SRAM 8 Mbytes ********************************************/
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44 /* Data Memory */
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45 D_MEM2 (RW) : org = 0x01100000 len = 0x00200000
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46 /**************************************************************************/
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47
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48 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
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49 /* Code & Variables Memory */
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50 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
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51 /**************************************************************************/
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52 }
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53
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54 /***********************************************/
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55 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
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56 /***********************************************/
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57
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58 /*
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59 * Since the bootloader directly calls the INT_Initialize() routine located
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60 * in int.s, this int.s code must always be mapped at the same address
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61 * (usually in the second flash sector). Its length is about 0x500 bytes.
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62 * Then comes the code that need to be loaded into the internal RAM.
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63 */
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64
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65 SECTIONS
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66 {
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67 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
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68 .monitor : > B_MEM /* Monitor Constants & Code */
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69 {
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70 $(CONST_BOOT_LIB)
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71 }
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72
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73 .inttext : {} > P_MEM1 /* int.s Code */
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74
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75 .bss_dar : > D_MEM1 /* DAR SWE Variables */
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76 {
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77 $(BSS_DAR_LIB)
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78 }
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79
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80 /*
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81 * The .bss section should not be split to ensure it is initialized to 0
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82 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
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83 * or in D_MEM2.
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84 */
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85
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86 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
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87 {
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88 $(BSS_BOOT_LIB)
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89 }
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90
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91 /*
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92 * All .bss sections, which must be mapped in internal RAM must be
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93 * grouped in order to initialized the corresponding memory to 0.
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94 * This initialization is done in int.s file before calling the Nucleus
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95 * routine.
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96 */
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97
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98 GROUP
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99 {
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100 S_D_Mem /* Label of start address of .bss section in Int. RAM */
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101 .DintMem
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102 {
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103
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104 /*
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105 * .bss sections of the application
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106 */
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107
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108 $(BSS_LIBS)
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109
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110 }
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111
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112 API_HISR_stack : {}
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113
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114 E_D_Mem /* Label of end address of .bss section in Int. RAM */
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115 } > S_MEM
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116
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117 /*
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118 * .text and .const sections which must be mapped in internal RAM.
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119 */
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120
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121 .ldfl : {} > P_MEM2 /* Used to know the start load address */
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122 GROUP load = P_MEM3 | P_MEM4, run = S_MEM
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123 {
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124 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
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125 .PIntMem
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126 {
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127 /*
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128 * .text and .const sections of the application.
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129 *
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130 * The .veneer sections correspond exactly to .text:v&n sections
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131 * implementing the veneer functions. The .text:v$n -> .veneer
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132 * translation is performed by PTOOL software when PTOOL_OPTIONS
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133 * environement variable is set to veneer_section.
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134 */
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135
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136 $(CONST_LIBS)
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137
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138 }
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139 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
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140 }
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141
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142 /*
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143 * The rest of the code is mapped in flash, however the trampolines
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144 * load address should be consistent with .text.
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145 */
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146 COMMENT2START
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147 `trampolines load = P_MEM3 | P_MEM4, run = S_MEM
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148 COMMENT2END
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149
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150 .text : {} >> P_MEM3 | P_MEM4 /* Code */
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151
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152 /*
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153 * The rest of the constants is mapped in flash.
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154 * The .cinit section should not be split.
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155 */
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156
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157 .cinit : {} > P_MEM4 /* Initialization Tables */
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158 .const : {} >> P_MEM4 | P_MEM3 /* Constant Data */
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159 KadaAPI : {} >> P_MEM4 | P_MEM3 /* ROMized CLDC */
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160
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161 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
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162
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163 .stackandheap : > D_MEM1 /* System Stacks, etc... */
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164 {
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165 /* Leave 20 32bit words for register pushes. */
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166 . = align(8);
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167 . += 20 * 4;
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168
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169 /* Stack for abort and/or undefined modes. */
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170 exception_stack = .;
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171
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172 /* Leave 38 32bit words for state saving on exceptions. */
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173 _xdump_buffer = .;
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174 . += 38 * 4;
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175 . = align(8);
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176
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177 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
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178 stack_segment = .;
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179 . += 0xB00;
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180 }
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181
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182 .data : {} > D_MEM1 /* Initialized Data */
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183 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
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184
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185 }