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comparison src/cs/system/main/gcc/exceptions.S @ 78:95ef11e76c5b

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src/cs/system/main/gcc: asm code pieced from Citrine
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 20 Jul 2018 06:46:56 +0000
parents
children 92fde62400ef
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77:6b6675a07b70 78:95ef11e76c5b
1 /*
2 * This module contains ARM exception handlers which used to be
3 * in chipsetsw/system/Main/int.s in TI's Leonardo code.
4 */
5
6 .section "except_stack","aw",%nobits
7 .balign 4
8 .space 512
9 .globl _Except_Stack_SP
10 _Except_Stack_SP:
11
12 .text
13 .code 32
14
15 @ layout of xdump buffer:
16 @ struct xdump_s {
17 @ long registers[16] // svc mode registers
18 @ long cpsr // svc mode CPSR
19 @ long exception // magic word + index of vector taken
20 @ long stack[20] // bottom 20 words of usr mode stack
21 @ }
22
23 .globl _arm_undefined
24 _arm_undefined:
25 @ store r12 for Xdump_buffer pointer, r11 for index
26 stmfd r13!,{r11,r12}
27 mov r11,#1
28 b save_regs
29
30 .globl _arm_swi
31 _arm_swi:
32 @ store r12 for Xdump_buffer pointer, r11 for index
33 stmfd r13!,{r11,r12}
34 mov r11,#2
35 b save_regs
36
37 .globl _arm_abort_prefetch
38 _arm_abort_prefetch:
39 @ store r12 for Xdump_buffer pointer, r11 for index
40 stmfd r13!,{r11,r12}
41 mov r11,#3
42 b save_regs
43
44 .globl _arm_abort_data
45 _arm_abort_data:
46 @ store r12 for Xdump_buffer pointer, r11 for index
47 stmfd r13!,{r11,r12}
48 mov r11,#4
49 b save_regs
50
51 .globl _arm_reserved
52 _arm_reserved:
53 ldr r13,=_Except_Stack_SP @ mode unknown
54 @ store r12 for Xdump_buffer pointer, r11 for index
55 stmfd r13!,{r11,r12}
56 mov r11,#5
57 b save_regs
58
59 save_regs:
60 ldr r12,=xdump_buffer
61 str r14,[r12,#4*15] @ save r14_abt (original PC) into r15 slot
62
63 stmia r12,{r0-r10} @ save unbanked registers (except r11 and r12)
64 ldmfd r13!,{r0,r1} @ get original r11 and r12
65 str r0,[r12,#4*11] @ save original r11
66 str r1,[r12,#4*12] @ save original r12
67 mrs r0,spsr @ get original psr
68 str r0,[r12,#4*16] @ save original cpsr
69
70 mrs r1,cpsr @ save mode psr
71 bic r2,r1,#0x1f @ psr with mode bits cleared
72 and r0,r0,#0x1f @ get original mode bits
73 add r0,r0,r2
74
75 msr cpsr,r0 @ move to pre-exception mode
76 str r13,[r12,#4*13] @ save original SP
77 str r14,[r12,#4*14] @ save original LR
78 msr cpsr,r1 @ restore mode psr
79
80 @ r11 has original index
81 orr r10,r11,#0xDE<<24 @ r10 = 0xDEAD0000 + index of vector taken
82 orr r10,r10,#0xAD<<16
83 str r10,[r12,#4*17] @ save magic + index
84
85 mov r0,r11 @ put index into 1st argument
86 b dar_exception