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comparison src/cs/system/main/gcc/bootentry.S @ 89:b398f288d20a

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src/cs/system/main/gcc/bootentry.S: written
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 20 Jul 2018 23:14:00 +0000
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children 2de9e5f46550
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88:b54e0f3759ff 89:b398f288d20a
1 /*
2 * This assembly module is our counterpart to TI's int.s: all boot entry
3 * point code that needs to be at the beginning of the flash resides here.
4 */
5
6 #include "asm_defs.h"
7 #include "fc-target.cfg"
8
9 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL)
10 /*
11 * Put something sensible in the boot ROM overlay area, just for the
12 * heck of it, or for extra robustness.
13 */
14 .section bootrom.overlay,"ax",%progbits
15 .code 32
16 .org 0
17 b BootROM_disabled_entry
18 #include "vectors.S"
19 BootROM_disabled_entry:
20 /* copy the boot ROM switch code to IRAM and jump to it */
21 ldr r4, =__romswitch_flash_addr
22 ldr r5, =__romswitch_ram_addr
23 ldr r2, =__romswitch_size
24 1: ldr r0, [r4], #4
25 str r0, [r5], #4
26 subs r2, r2, #4
27 bhi 1b
28 ldr pc, =__romswitch_ram_addr
29
30 .section bootrom.switch,"ax",%progbits
31 .code 32
32 .org 0
33 @ enable the Calypso boot ROM
34 ldr r1, =0xFFFFFB10
35 mov r2, #0x0100
36 strh r2, [r1]
37 @ jump to it!
38 mov pc, #0
39 #endif
40
41 .section .inttext,"ax",%progbits
42 .code 32
43
44 #ifdef FLASH
45 .org 0
46 #ifndef CONFIG_TARGET_COMPAL
47 /* sane targets with Calypso boot ROM enabled by the PCB wiring */
48 /* provide the necessary magic words for the boot ROM */
49 .word 0
50 .word _Firmware_boot_entry
51 #elif defined(CONFIG_TARGET_C139) || defined(CONFIG_TARGET_C11X)
52 /*
53 * On this target we'll put a patched version of Compal's boot code in
54 * flash sector 0 (the brickable one); the main fw images will then be
55 * flashed starting at 0x10000, which is where our modified boot code
56 * expects them to be. The interface between our hacked boot code and
57 * the main fw has been made to mimic TI's TCS211 reference fw.
58 */
59 #include "vectors.S"
60 .org 0x58 /* put _Firmware_boot_entry at 0x10058 */
61 #elif defined(CONFIG_TARGET_C155)
62 /*
63 * On this target the hand-off point between the bootloader and the main
64 * fw image coincides with a flash erase block boundary, thus we can reuse
65 * the original bootloader without having to reflash the brickable sector
66 * at all. The following bits will appear at 0x20000.
67 */
68 .asciz "FreeCalypso firmware for C155/156 target"
69 .org 0xE0
70 /* C155/156 bootloader jumps here */
71 b _Firmware_boot_entry
72 #include "vectors.S"
73 #else
74 #error "Unsupported flash boot configuration"
75 #endif
76 #endif
77
78 /* definitions from TI's int.s */
79
80 #define IRQ_STACK_SIZE 128
81 #define FIQ_STACK_SIZE 512
82 #define SYSTEM_SIZE 1024
83 #define TIMER_SIZE 1024
84 #define TIMER_PRIORITY 2
85
86 .globl _Firmware_boot_entry
87 _Firmware_boot_entry:
88 @ TI's code from int.s follows
89
90 @
91 @ Configure DPLL register with reset value
92 @
93 ldr r1,DPLL_CNTRL_REG @ Load address of DPLL register in R1
94 ldrh r2,DPLL_CONTROL_RST @ Load DPLL reset value in R2
95 strh r2,[r1] @ Store DPLL reset value in DPLL register
96
97 @
98 @ Wait that DPLL goes in BYPASS mode
99 @
100 Wait_DPLL_Bypass:
101 ldr r2,[r1] @ Load DPLL register
102 and r2,r2,#1 @ Perform a mask on bit 0
103 cmp r2,#1 @ Compare DPLL lock bit
104 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
105
106 @
107 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
108 @ generate ARM clock with division factor of 1.
109 @
110 ldr r1,CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
111 ldrh r2,CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
112 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
113
114 @
115 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
116 @
117 ldr r1,EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
118 ldrh r2,ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
119 ldrh r0,[r1] @ Load Extra Control register CONF in r0
120 and r0,r0,r2 @ Enable DU module
121 strh r0,[r1] @ Store configuration in Extra Control register CONF
122
123 @
124 @ Disable all MPU protections
125 @
126 ldr r1,MPU_CTL_REG @ Load address of MPU_CTL register
127 ldrh r2,MPU_CTL_RST @ Load reset value of MPU_CTL register
128 strh r2,[r1] @ Store reset value of MPU_CTL register
129
130 @ MEMIF timing setup
131
132 ldr r1,addrCS0
133 ldrh r2,CS0_MEM_REG @ ROM initialization
134 strh r2,[r1] @ CS0
135
136 ldrh r2,CS1_MEM_REG @ RAM Initialization
137 strh r2,[r1,#2] @ CS1
138
139 ldrh r2,CS2_MEM_REG @ RAM Initialization
140 strh r2,[r1,#4] @ CS2
141
142 ldrh r2,CS3_MEM_REG @ Parallel I/O on B-Sample
143 strh r2,[r1,#6] @ CS3 (unused on EVA4?)
144
145 ldrh r2,CS4_MEM_REG @ Latch on B-Sample
146 strh r2,[r1,#0xa] @ CS4 (unused on EVA4)
147
148 ldrh r2,CS6_MEM_REG @ Internal SRAM initialization
149 strh r2,[r1,#0xc] @ CS6 Internal RAM
150
151 ldrh r2,CS7_MEM_REG @ Internal SRAM initialization
152 strh r2,[r1,#0x8] @ CS7 Internal Boot ROM
153
154 ldrh r2,CTL_MEM_REG @ API-RHEA configuration
155 strh r2,[r1,#0xe]
156
157 @ enable ADD22
158
159 ldr r1,EX_MPU_CONF_REG
160 ldrh r2,[r1]
161 ldr r0,EX_FLASH_VALUE
162 orr r0, r0, r2
163 strh r0,[r1]
164
165 /* Ensure that the processor is in supervisor mode. */
166
167 MRS a1,CPSR @ Pickup current CPSR
168 BIC a1,a1,#MODE_MASK @ Clear the mode bits
169 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
170 ORR a1,a1,#LOCKOUT @ Ensure IRQ and FIQ interrupts are
171 @ locked out
172 MSR CPSR,a1 @ Setup the new CPSR
173
174 /*
175 * FreeCalypso Selenite: if this is a flash build,
176 * copy IRAM code and .data from flash to RAM.
177 */
178
179 #ifdef FLASH
180 /* copy iram.text to where it's supposed to be */
181 ldr r8, =__iramtext_flash_addr
182 ldr r9, =__iramtext_ram_addr
183 ldr r10, =__iramtext_size
184 1: ldmia r8!, {r0-r7}
185 stmia r9!, {r0-r7}
186 subs r10, r10, #0x20
187 bhi 1b
188 /* likewise copy .data from flash to XRAM */
189 ldr r8, =__initdata_flash_addr
190 ldr r9, =__initdata_ram_addr
191 ldr r10, =__initdata_size
192 1: ldmia r8!, {r0-r7}
193 stmia r9!, {r0-r7}
194 subs r10, r10, #0x20
195 bhi 1b
196 #endif
197
198 /* Both flash and XRAM builds: zero .bss */
199
200 ldr r0, =__intbss_start
201 ldr r1, =__intbss_size
202 bl bzero
203 ldr r0, =__extbss_start
204 ldr r1, =__extbss_size
205 bl bzero
206
207 @ TI's int.s code continues
208
209 @
210 @ Initialize the system stack pointers. This is done after the BSS is
211 @ cleared because the TCD_System_Stack pointer is a BSS variable! It is
212 @ assumed that the .cmd file is written to direct where these stacks should
213 @ be allocated and to align them on double word boundaries.
214 @
215 LDR a1,StackSegment @ Pickup the begining address from .cmd file
216 @ (is aligned on 8 byte boundary)
217 MOV a2,#SYSTEM_SIZE @ Pickup system stack size
218 SUB a2,a2,#4 @ Subtract one word for first addr
219 ADD a3,a1,a2 @ Build start of system stack area
220 MOV v7,a1 @ Setup initial stack limit
221 LDR a4,System_Limit @ Pickup system stack limit address
222 STR v7,[a4, #0] @ Save stack limit
223 MOV sp,a3 @ Setup initial stack pointer
224 LDR a4,System_Stack @ Pickup system stack address
225 STR sp,[a4, #0] @ Save stack pointer
226 MOV a2,#IRQ_STACK_SIZE @ Pickup IRQ stack size in bytes
227 ADD a3,a3,a2 @ Allocate IRQ stack area
228 MRS a1,CPSR @ Pickup current CPSR
229 BIC a1,a1,#MODE_MASK @ Clear the mode bits
230 ORR a1,a1,#IRQ_MODE @ Set the IRQ mode bits
231 MSR CPSR,a1 @ Move to IRQ mode
232 MOV sp,a3 @ Setup IRQ stack pointer
233 MOV a2,#FIQ_STACK_SIZE @ Pickup FIQ stack size in bytes
234 ADD a3,a3,a2 @ Allocate FIQ stack area
235 MRS a1,CPSR @ Pickup current CPSR
236 BIC a1,a1,#MODE_MASK @ Clear the mode bits
237 ORR a1,a1,#FIQ_MODE @ Set the FIQ mode bits
238 MSR CPSR,a1 @ Move to the FIQ mode
239 MOV sp,a3 @ Setup FIQ stack pointer
240
241 MRS a1,CPSR @ Pickup current CPSR
242 BIC a1,a1,#MODE_MASK @ Clear the mode bits
243 ORR a1,a1,#ABORT_MODE @ Set the Abort mode bits
244 MSR CPSR,a1 @ Move to the Abort mode
245 LDR sp,Exception_Stack @ Setup Abort stack pointer
246
247 MRS a1,CPSR @ Pickup current CPSR
248 BIC a1,a1,#MODE_MASK @ Clear the mode bits
249 ORR a1,a1,#UNDEF_MODE @ Set the Undefined mode bits
250 MSR CPSR,a1 @ Move to the Undefined mode
251 LDR sp,Exception_Stack @ Setup Undefined stack pointer
252 @ (should never be used)
253
254 @ go to Supervisor Mode
255 MRS a1,CPSR @ Pickup current CPSR
256 BIC a1,a1,#MODE_MASK @ Clear mode bits
257 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
258 MSR CPSR,a1 @ All interrupt stacks are setup,
259 @ return to supervisor mode
260 @
261 @ /* Define the global data structures that need to be initialized by this
262 @ routine. These structures are used to define the system timer
263 @ management HISR. */
264 @ TMD_HISR_Stack_Ptr = (VOID *) a3;
265 @ TMD_HISR_Stack_Size = TIMER_SIZE;
266 @ TMD_HISR_Priority = TIMER_PRIORITY;
267 @
268 @ TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
269 @ area. The Timer HISR (called "SYSTEM H") and its related stack will be created
270 @ in TMI_Initialize(). The current stack pointer will be set at the bottom (the
271 @ lowest address) of the expected area.
272
273 LDR a4,HISR_Stack_Ptr @ Pickup variable's address
274 ADD a3,a3,#4 @ Increment to next available word
275 STR a3,[a4, #0] @ Setup timer HISR stack pointer
276 MOV a2,#TIMER_SIZE @ Pickup the timer HISR stack size
277 BIC a2,a2,#3 @ Insure word alignment
278 ADD a3,a3,a2 @ Allocate the timer HISR stack
279 @ from available memory
280 LDR a4,HISR_Stack_Size @ Pickup variable's address
281 STR a2,[a4, #0] @ Setup timer HISR stack size
282 MOV a2,#TIMER_PRIORITY @ Pickup timer HISR priority (0-2)
283 LDR a4,HISR_Priority @ Pickup variable's address
284 STR a2,[a4, #0] @ Setup timer HISR priority
285
286 /* TI's original code called f_load_int_mem() at this point */
287 /* let's do our internal ROM enable step here */
288
289 ldr r1, EXTRA_CONTROL_REG
290 ldrh r0, [r1, #0]
291 bic r0, #0x0300
292 orr r0, #0x0100
293 strh r0, [r1, #0]
294
295 @ We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
296 @ checking the status of the stacks later.
297 @ inputs:
298 @ a3 still has the bottom of all four stacks and is aligned.
299 @ algorithm:
300 @ We start from the top of all four stacks (*System_Limit), which is
301 @ necessarily aligned. We store 0xFEFEFEFE until we have filled the
302 @ bottom of the fourth stack
303 @ outputs:
304 @ memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
305 @ a3 still has the bottom of all four stacks
306
307 LDR a2,System_Limit @ pickup system stack limit address
308 LDR a1,[a2] @ a1 = StackSegment
309 LDR a4,=0xFEFEFEFE
310
311 fill_stack:
312 STR a4,[a1],#4 @ store a word and increment by four
313 CMP a1,a3 @ is this the last address?
314 BLT fill_stack @ if not, loop back
315
316 @
317 @ /* Call INC_Initialize with a pointer to the first available memory
318 @ address after the compiler's global data. This memory may be used
319 @ by the application. */
320 @ INC_Initialize(first_available_memory);
321 @
322 MOV a1,a3 @ Pass the first available memory
323 B INC_Initialize @ to high-level initialization
324
325 @ literal pool from int.s
326
327 addrCS0: .word 0xfffffb00 @ CS0 address space
328
329 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
330 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
331
332 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
333 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
334 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
335 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
336
337 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
338 @ Use DPLL, Divide by 1
339 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
340 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
341 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
342 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
343
344 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
345 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
346 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
347 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
348 CS4_MEM_REG: .short 0xe85 @ default reset value
349 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
350 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
351 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
352
353 StackSegment:
354 .word _Stack_segment_start
355
356 System_Limit:
357 .word TCT_System_Limit
358
359 System_Stack:
360 .word TCD_System_Stack
361
362 HISR_Stack_Ptr:
363 .word TMD_HISR_Stack_Ptr
364
365 HISR_Stack_Size:
366 .word TMD_HISR_Stack_Size
367
368 HISR_Priority:
369 .word TMD_HISR_Priority
370
371 Exception_Stack:
372 .word _Except_Stack_SP