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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : clkm.h
12
13 Description : Header file for the CLKM module
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.19
20
21 Date and time : 07/01/03
22
23 Previous delta : 10/19/01 15:25:25
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h
26
27 Sccs Id (SID) : '@(#) clkm.h 1.10 10/23/01 14:34:54 '
28
29
30 *****************************************************************************/
31
32 #include "l1sw.cfg"
33 #include "chipset.cfg"
34 #include "board.cfg"
35
36 #if (OP_L1_STANDALONE == 0)
37 #include "main/sys_types.h"
38 #else
39 #include "sys_types.h"
40 #endif
41
42 #if (CHIPSET == 12)
43 #include "sys_map.h"
44 #endif
45
46 #if (CHIPSET == 12)
47 #define CLKM_ARM_CLK C_MAP_CLKM_BASE /* CLKM registers addr. */
48 #else
49 #define CLKM_ARM_CLK MEM_CLKM_ADDR /* CLKM ARM CLock Control reg.*/
50 #endif
51 #define CLKM_MCLK_EN 0x0001
52
53
54 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
55 #define MASK_CLKIN 0x0006
56 #endif
57
58 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
59 #define CLKM_CLKIN0 0x0002 // Mask to select between DPLL and VTCXO or CLKIN
60 #else
61 #define CLKM_LOW_FRQ 0x0002 // Mask to select low frequency input CLK_32K
62 #endif
63 #define CLKM_CLKIN_SEL 0x0004 // Mask to select between VTCXO and CLKIN
64
65 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
66 #define CLKM_ARM_MCLK_XP5 0x0008 // Mask to enable the 1.5 or 2.5 division factor
67 #define CLKM_MCLK_DIV 0x0070 // Mask to configure the division factor
68 #else
69 #define MASK_ARM_MCLK_1P5 0x0008 // Mask to enable the 1.5 division factor
70 #define CLKM_MCLK_DIV 0x0030 // Mask to configure the division factor
71 #endif
72
73 #define CLKM_DEEP_PWR 0x0f00 // Mask to configure deep power
74 #define CLKM_DEEP_SLEEP 0x1000 // Mask to configure deep sleep
75
76 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
77 #define CLKM_SEL_DPLL 0x0000 // Selection of DPLL for ARM clock generation
78 #define CLKM_SEL_VTCXO 0x0001 // Selection of VTCXO for ARM clock generation
79 #define CLKM_SEL_CLKIN 0x0003 // Selection of CLKIN for ARM clock generation
80
81 #define CLKM_ENABLE_XP5 0x0001 // Enable 1.5 or 2.5 division factor
82 #define CLKM_DISABLE_XP5 0x0000 // Disable 1.5 or 2.5 division factor
83
84 #define CLKM_ARM_MCLK_DIV_OFFSET 4 // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
85
86 #define CLKM_ARM_CLK_RESET 0x1081 // Reset value of CNTL_ARM_CLK register
87 #endif
88
89 #if (CHIPSET == 12)
90 #define CLKM_CNTL_ARM_CLK (C_MAP_CLKM_BASE + 0x00)
91 #define CLKM_CNTL_CLK (C_MAP_CLKM_BASE + 2) /* CLKM Clock Control reg. */
92 #else
93 #define CLKM_CNTL_ARM_CLK (MEM_CLKM_ADDR + 0x00)
94 #define CLKM_CNTL_CLK (MEM_CLKM_ADDR + 2) /* CLKM Clock Control reg. */
95 #endif
96
97 #define CLKM_IRQ_DIS 0x0001 // IRQ clock is disabled and enabled according to the sleep command
98 #define CLKM_BRIDGE_DIS 0x0002 // BRIDGE clock is disabled and enabled according to the sleep command
99 #define CLKM_TIMER_DIS 0x0004 // TIMER clock is disabled and enabled according to the sleep command
100 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
101 #define CLKM_DPLL_DIS 0x0008 // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
102 #else
103 #define CLKM_PLL_SEL 0x0008 // CLKIN input is connected to the PLL
104 #endif
105 #define CLKM_CLKOUT_EN 0x0010 // Enable CLKOUT(2:0) output clocks
106 #if (CHIPSET == 4)
107 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
108 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
109 #elif (CHIPSET == 6)
110 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
111 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
112 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
113 #define CLKM_VCLKOUT_2 0x0040 // VTCXO is divided by 2
114 #define CLKM_VTCXO_2 0x0080 // Input clock to DPLL is divided by 2
115 #endif
116
117 #if (CHIPSET == 12)
118 #define CLKM_CNTL_RST (C_MAP_CLKM_BASE + 4) /* CLKM Reset Control reg. */
119 #else
120 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */
121 #endif
122 #define CLKM_LEAD_RST 0x0002
123 #define CLKM_EXT_RST 0x0004
124
125 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
126 #define DPLL_LOCK 0x0001 // Mask of DPLL lock status
127 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration
128 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL
129 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration
130 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration
131
132 #define DPLL_BYPASS_DIV_1 0x00 // Configuration of bypass mode divided by 1
133 #define DPLL_BYPASS_DIV_2 0x01 // Configuration of bypass mode divided by 2
134 #define DPLL_BYPASS_DIV_4 0x10 // Configuration of bypass mode divided by 4
135
136 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration
137 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration
138 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration
139
140 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked
141 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked
142 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked
143 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked
144
145 #else
146 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */
147 #define CLKM_PLONOFF 0x0001 // PLL enable signal
148 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration
149 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection
150 #define CLKM_PLDIV 0x0040 // Mask of multiply factor configuration
151 #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
152 #endif
153
154 #if (CHIPSET == 12)
155 #define CLKM_CNTL_CLK_DSP (C_MAP_CLKM_BASE + 0x8A) /* CLKM CNTL_CLK_REG register */
156
157 #define CLKM_NB_DSP_DIV_VALUE 4
158
159 #define CLKM_DSP_DIV_1 0x00
160 #define CLKM_DSP_DIV_1_5 0x01
161 #define CLKM_DSP_DIV_2 0x02
162 #define CLKM_DSP_DIV_3 0x03
163
164 #define CLKM_DSP_DIV_MASK 0x0003
165
166 extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
167
168 /*---------------------------------------------------------------
169 * CLKM_DSP_DIV_FACTOR()
170 *--------------------------------------------------------------
171 * Parameters : none
172 * Return : none
173 * Functionality : Set the DSP division factor
174 *--------------------------------------------------------------*/
175
176 #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)
177
178
179 /*---------------------------------------------------------------
180 * CLKM_READ_DSP_DIV()
181 *--------------------------------------------------------------
182 * Parameters : none
183 * Return : none
184 * Functionality : Read DSP division factor
185 *--------------------------------------------------------------*/
186
187 #define CLKM_READ_DSP_DIV ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
188
189 #define CLKM_GET_DSP_DIV_VALUE dsp_div_value[CLKM_READ_DSP_DIV]
190
191 #endif
192
193
194 /*---------------------------------------------------------------
195 * CLKM_SETLEADRESET()
196 *--------------------------------------------------------------
197 * Parameters : none
198 * Return : none
199 * Functionality : Set the LEAD reset signal
200 *--------------------------------------------------------------*/
201
202 #define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)
203
204 /*---------------------------------------------------------------
205 * CLKM_RELEASELEADRESET()
206 *--------------------------------------------------------------
207 * Parameters : none
208 * Return : none
209 * Functionality : Release the LEAD reset signal
210 *--------------------------------------------------------------*/
211
212 #define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)
213
214 /*---------------------------------------------------------------
215 * CLKM_SETEXTRESET()
216 *--------------------------------------------------------------
217 * Parameters : none
218 * Return : none
219 * Functionality : Set the external reset signal
220 *--------------------------------------------------------------*/
221
222 #define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)
223
224 /*---------------------------------------------------------------
225 * CLKM_CLEAREXTRESET()
226 *--------------------------------------------------------------
227 * Parameters : none
228 * Return : none
229 * Functionality : Clear the external reset signal
230 *--------------------------------------------------------------*/
231
232 #define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)
233
234
235 /*---------------------------------------------------------------
236 * CLKM_POWERDOWNARM()
237 *--------------------------------------------------------------
238 * Parameters : none
239 * Return : none
240 * Functionality : Power down the ARM mcu
241 *--------------------------------------------------------------*/
242 #define CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)
243
244 /*---------------------------------------------------------------
245 * CLKM_SET1P5()
246 *--------------------------------------------------------------
247 * Parameters : none
248 * Return : none
249 * Functionality : Set ARM_MCLK_1P5 bit
250 *--------------------------------------------------------------*/
251
252 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
253 #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
254 #else
255 #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
256 #endif
257
258 /*---------------------------------------------------------------
259 * CLKM_RESET1P5()
260 *--------------------------------------------------------------
261 * Parameters : none
262 * Return : none
263 * Functionality : Reset ARM_MCLK_1P5 bit
264 *--------------------------------------------------------------*/
265
266 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
267 #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
268 #else
269 #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
270 #endif
271
272 /*---------------------------------------------------------------
273 * CLKM_INITCNTL()
274 *--------------------------------------------------------------
275 * Parameters : value to write in the CNTL register
276 * Return : none
277 * Functionality :Initialize the CLKM Control Clock register
278 *--------------------------------------------------------------*/
279
280 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= value)
281
282
283 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
284 /*---------------------------------------------------------------
285 * CLKM_INITLEADPLL()
286 *--------------------------------------------------------------
287 * Parameters : value to write in the CNTL_PLL LEAD register
288 * Return : none
289 * Functionality :Initialize LEAD PLL control register
290 *--------------------------------------------------------------*/
291
292 #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
293 #endif
294
295 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
296 /*--------------------------------------------------------------
297 * CLKM_DPLL_SWITH_OFF_MODE_CONFIG()
298 *--------------------------------------------------------------
299 * Parameters : None
300 * Return : none
301 * Functionality : Configure DPLL switch off mode
302 *--------------------------------------------------------------*/
303
304 #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
305 (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
306
307 /*--------------------------------------------------------------
308 * CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG()
309 *--------------------------------------------------------------
310 * Parameters : None
311 * Return : none
312 * Functionality : Reset configuration of DPLL switch off mode
313 *--------------------------------------------------------------*/
314
315 #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
316 ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
317
318 /*--------------------------------------------------------------
319 * CLKM_FORCE_API_HOM_IN_IDLE3()
320 *--------------------------------------------------------------
321 * Parameters : None
322 * Return : none
323 * Functionality : SAM/HOM wait-state register force to HOM when
324 * DSP is in IDLE3 mode */
325 /*--------------------------------------------------------------*/
326
327 #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))
328
329 #if (CHIPSET == 4)
330 /*--------------------------------------------------------------
331 * CLKM_USE_VTCXO_26MHZ()
332 *--------------------------------------------------------------
333 * Parameters : None
334 * Return : none
335 * Functionality : Divide by 2 the clock used by the peripheral
336 * when using external VTCXO at 26 MHz instead
337 * of 13MHz
338 *--------------------------------------------------------------*/
339
340 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))
341
342 /*--------------------------------------------------------------
343 * CLKM_UNUSED_VTCXO_26MHZ()
344 *--------------------------------------------------------------
345 * Parameters : None
346 * Return : none
347 * Functionality : Use VTCXO=13MHz
348 *--------------------------------------------------------------*/
349
350 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
351 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
352 /*--------------------------------------------------------------
353 * CLKM_UNUSED_VTCXO_26MHZ()
354 *--------------------------------------------------------------
355 * Parameters : None
356 * Return : none
357 * Functionality : Use VTCXO=13MHz
358 *--------------------------------------------------------------*/
359
360 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))
361
362 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
363 #endif
364
365 #if (CHIPSET == 12)
366 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE |= DPLL_PLL_ENABLE)
367 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE &= ~DPLL_PLL_ENABLE)
368
369 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
370 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) &= ~DPLL_BYPASS_DIV; \
371 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
372 }
373
374 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
375 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
376 *((volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
377 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
378 }
379
380 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
381 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
382 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_LOCK)
383 #else
384 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
385 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
386
387 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
388 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
389 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
390 }
391
392 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
393 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
394 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
395 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
396 }
397
398 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
399 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
400 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)
401 #endif /* (CHIPSET == 12) */
402
403
404 #endif
405
406 /* ----- Prototypes ----- */
407
408 #if (BOARD == 34)
409 void CLKM_InitARMClock(int src, int div);
410 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
411 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
412 #else
413 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
414 #endif
415
416 #if (BOARD == 34)
417 void CLKM_SetMclkDiv(int div);
418 void CLKM_EnableDPLL(int enable);
419 void CLKM_EnableSharedMemClock(int enable);
420 void CLKM_InitLeadClock(int onoff, int mul, int ndiv, int div);
421 #endif
422
423 void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
424 void initialize_wait_loop(void);
425 SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);
426