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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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1 /* @(#) nom : sys_inth.h SID: 1.2 date : 05/23/03 */
2 /* Filename: sys_inth.h */
3 /* Version: 1.2 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Francois AMAND
10 *
11 *
12 * Important Note
13 * --------------
14 *
15 * This S/W is a preliminary version. It contains information on a product
16 * under development and is issued for evaluation purposes only. Features
17 * characteristics, data and other information are subject to change.
18 *
19 * The S/W is furnished under Non Disclosure Agreement and may be used or
20 * copied only in accordance with the terms of the agreement. It is an offence
21 * to copy the software in any way except as specifically set out in the
22 * agreement. No part of this document may be reproduced or transmitted in any
23 * form or by any means, electronic or mechanical, including photocopying and
24 * recording, for any purpose without the express written permission of Texas
25 * Instruments Inc.
26 *
27 ******************************************************************************
28 *
29 * FILE NAME: sys_inth.h
30 *
31 *
32 * PURPOSE: Header file for the Interrupt Handler Driver.
33 *
34 *
35 * FILE REFERENCES:
36 *
37 * Name IO Description
38 * ------------- -- ---------------------------------------------
39 *
40 *
41 *
42 * EXTERNAL VARIABLES:
43 *
44 * Source:
45 *
46 * Name Type IO Description
47 * ------------- --------------- -- ------------------------------
48 *
49 *
50 *
51 * EXTERNAL REFERENCES:
52 *
53 * Name Description
54 * ------------------ -------------------------------------------------------
55 *
56 *
57 *
58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
59 *
60 *
61 *
62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
63 *
64 *
65 *
66 * NOTES:
67 *
68 *
69 *
70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
71 *
72 *
73 *
74 *
75 * DEVELOPMENT HISTORY:
76 *
77 * Date Name(s) Version Description
78 * ----------- -------------- ------- -------------------------------------
79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
80 *
81 * ALGORITHM:
82 *
83 *
84 *****************************************************************************/
85
86 #include "l1sw.cfg"
87 #include "chipset.cfg"
88
89 #if (CHIPSET == 12)
90
91 #ifndef __SYS_INTH_H__
92 #define __SYS_INTH_H__
93
94 #if (OP_L1_STANDALONE == 0)
95 #include "main/sys_types.h"
96 #else
97 #include "sys_types.h"
98 #endif
99 #include "sys_map.h"
100
101
102 /*
103 * Driver version
104 */
105 #define C_INTH_DRIVER_VERSION 0x0001
106
107
108 /*
109 * Number of interrupts
110 */
111 #define C_INTH_NUM_INT 32
112 #define C_INTH_2ND_NUM_INT 5
113
114 #define C_INTH_NB_INTERRUPT (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)
115
116
117 /*
118 * Main INTH : Interrupt bit numbers
119 */
120 #define C_INTH_WATCHDOG_IT 0
121 #define C_INTH_TIMER1_IT 1
122 #define C_INTH_TIMER2_IT 2
123 #define C_INTH_TSP_RECEIVE_IT 3
124 #define C_INTH_FRAME_IT 4
125 #define C_INTH_PAGE_IT 5
126 #define C_INTH_SIM_IT 6
127 #define C_INTH_UART_MODEM1_IT 7
128 #define C_INTH_KEYBOARD_IT 8
129 #define C_INTH_RTC_TIMER_IT 9
130 #define C_INTH_RTC_ALARM_IT 10
131 #define C_INTH_ULPD_GAUGING_IT 11
132 #define C_INTH_ABB_IRQ_IT 12
133 #define C_INTH_SPIv 13
134 #define C_INTH_DMA_IT 14
135 #define C_INTH_API_IT 15
136 #define C_INTH_GPIO_IT 16
137 #define C_INTH_ABB_FIQ_IT 17
138 #define C_INTH_UART_IRDA_IT 18
139 #define C_INTH_TGSM_IT 19
140 #define C_INTH_GEA_IT 20
141 #define C_INTH_EXT_IRQ1_IT 21
142 #define C_INTH_EXT_IRQ2_IT 22
143 #define C_INTH_USIM_CD_IT 23
144 #define C_INTH_USIM_IT 24
145 #define C_INTH_LCD_IT 25
146 #define C_INTH_USB_IT 26
147 #define C_INTH_MMC_SD_MS_IT 27
148 #define C_INTH_UART_MODEM2_IT 28
149 #define C_INTH_2ND_INTH_IT 29
150 #define C_INTH_I2C_IT 30
151 #define C_INTH_NAND_FLASH_IT 31
152
153 /*
154 * Second INTH : Interrupt bit numbers
155 */
156 #define C_INTH_RNG_IT 32
157 #define C_INTH_SHA1_MD5_IT 33
158 #define C_INTH_EMPU_IT 34
159 #define C_INTH_SEC_DMA_IT 35
160 #define C_INTH_SEC_TIMER_IT 36
161
162
163 /*
164 * Address of the Main interrupt handler registers
165 */
166 #define C_INTH_IT_REG1 C_MAP_INTH_BASE /* INTH IT register 1 */
167 #define C_INTH_IT_REG2 (C_MAP_INTH_BASE + 0x02) /* INTH IT register 2 */
168 #define C_INTH_MASK_REG1 (C_MAP_INTH_BASE + 0x08) /* INTH mask register 1 */
169 #define C_INTH_MASK_REG2 (C_MAP_INTH_BASE + 0x0a) /* INTH mask register 2 */
170 #define C_INTH_B_IRQ_REG (C_MAP_INTH_BASE + 0x10) /* INTH source binary IRQ reg. */
171 #define C_INTH_B_FIQ_REG (C_MAP_INTH_BASE + 0x12) /* INTH source binary FIQ reg. */
172 #define C_INTH_CTRL_REG (C_MAP_INTH_BASE + 0x14) /* INTH control register */
173 #define C_INTH_EXT_REG (C_MAP_INTH_BASE + 0x20) /* INTH 1st external int. reg. */
174
175 /*
176 * Address of the Second interrupt handler registers
177 */
178 #define C_INTH2_IT_REG1 C_MAP_INTH_SEC_BASE /* INTH IT register 1 */
179 #define C_INTH2_MASK_REG1 (C_MAP_INTH_SEC_BASE + 0x08) /* INTH mask register 1 */
180 #define C_INTH2_B_IRQ_REG (C_MAP_INTH_SEC_BASE + 0x10) /* INTH source binary IRQ reg. */
181 #define C_INTH2_CTRL_REG (C_MAP_INTH_SEC_BASE + 0x14) /* INTH control register */
182 #define C_INTH2_EXT_REG (C_MAP_INTH_SEC_BASE + 0x20) /* INTH 1st external int. reg. */
183
184
185 /*
186 * INTH_B_x_REG definition
187 */
188 #define C_INTH_SRC_NUM 0x001f
189 #define C_INTH2_SRC_NUM 0x0007
190
191 /*
192 * ILR_IRQx_REG definition
193 */
194 #define C_INTH_IRQ 0
195 #define C_INTH_FIQ 1
196
197 #define C_INTH_LEVEL 0
198 #define C_INTH_EDGE 1
199
200
201
202 /****************************************************************************
203 * MACRO DEFINITION
204 ***************************************************************************/
205
206 /****************************************************************************
207 *
208 * MACRO NAME: F_INTH_ENABLE_ONE_IT
209 * Enable the interrupt specified in argument.
210 *
211 *
212 * ARGUMENT LIST:
213 *
214 * Argument Description
215 * ------------ ----------------------------------------------------------
216 * d_it Interrupt index
217 *
218 * RETURN VALUE: None
219 *
220 ***************************************************************************/
221
222 #define F_INTH_ENABLE_ONE_IT(d_it) { \
223 if (d_it < 16) \
224 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 &= ~(1 << d_it); \
225 else if (d_it < C_INTH_NUM_INT) \
226 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 &= ~(1 << (d_it-16)); \
227 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \
228 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 &= ~(1 << (d_it-32)); \
229 }
230
231
232
233 /****************************************************************************
234 *
235 * MACRO NAME: F_INTH_DISABLE_ONE_IT
236 * Disable the interrupt specified in argument.
237 *
238 *
239 * ARGUMENT LIST:
240 *
241 * Argument Description
242 * ------------ ----------------------------------------------------------
243 * d_it Interrupt index
244 *
245 * RETURN VALUE: None
246 *
247 ***************************************************************************/
248
249 #define F_INTH_DISABLE_ONE_IT(d_it) { \
250 if (d_it < 16) \
251 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 |= (1 << d_it); \
252 else if (d_it < C_INTH_NUM_INT) \
253 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 |= (1 << (d_it-16)); \
254 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \
255 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 |= (1 << (d_it-32)); \
256 }
257
258
259
260 /****************************************************************************
261 *
262 * MACRO NAME: F_INTH_DISABLE_ALL_IT
263 * Disable all interrupts.
264 *
265 *
266 * ARGUMENT LIST:
267 *
268 * Argument Description
269 * ------------ ----------------------------------------------------------
270 *
271 * RETURN VALUE: None
272 *
273 ***************************************************************************/
274
275 #define F_INTH_DISABLE_ALL_IT { \
276 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 = 0xffff; \
277 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 = 0xffff; \
278 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 = 0x001f; \
279 }
280
281
282
283 /****************************************************************************
284 *
285 * MACRO NAME: F_INTH_RESET_ALL_IT
286 * Reset all interrupts.
287 *
288 *
289 * ARGUMENT LIST:
290 *
291 * Argument Description
292 * ------------ ----------------------------------------------------------
293 *
294 * RETURN VALUE: None
295 *
296 ***************************************************************************/
297
298 #define F_INTH_RESET_ALL_IT { \
299 * (volatile SYS_UWORD16 *) C_INTH_IT_REG1 &= 0x0000; \
300 * (volatile SYS_UWORD16 *) C_INTH_IT_REG2 &= 0x0000; \
301 * (volatile SYS_UWORD16 *) C_INTH2_IT_REG1 &= 0x0000; \
302 }
303
304
305 /****************************************************************************
306 *
307 * MACRO NAME: F_INTH_RESET_ONE_IT
308 * Reset the interrupt specified in argument.
309 *
310 *
311 * ARGUMENT LIST:
312 *
313 * Argument Description
314 * ------------ ----------------------------------------------------------
315 * d_it Interrupt index
316 *
317 * RETURN VALUE: None
318 *
319 ***************************************************************************/
320
321 #define F_INTH_RESET_ONE_IT(d_it) { \
322 if (d_it < 16) \
323 * (volatile SYS_UWORD16 *) C_INTH_IT_REG1 &= ~(1 << d_it); \
324 else if (d_it < C_INTH_NUM_INT) \
325 * (volatile SYS_UWORD16 *) C_INTH_IT_REG2 &= ~(1 << (d_it-16)); \
326 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \
327 * (volatile SYS_UWORD16 *) C_INTH2_IT_REG1 &= ~(1 << (d_it-32)); \
328 }
329
330 /****************************************************************************
331 *
332 * MACRO NAME: F_INTH_VALID_NEXT
333 * Valid next interrupt on the main interrupt handler.
334 *
335 *
336 * ARGUMENT LIST:
337 *
338 * Argument Description
339 * ------------ ----------------------------------------------------------
340 * d_fiq_nirq Source of the interrupt IRQ or FIQ
341 *
342 * RETURN VALUE: None
343 *
344 ***************************************************************************/
345
346 #define F_INTH_VALID_NEXT(d_fiq_nirq) * (volatile SYS_UWORD16 *) C_INTH_CTRL_REG |= (1 << d_fiq_nirq)
347
348
349
350 /****************************************************************************
351 *
352 * MACRO NAME: F_INTH2_VALID_NEXT
353 * Valid next interrupt on the 2nd level interrupt handler.
354 *
355 *
356 * ARGUMENT LIST:
357 *
358 * Argument Description
359 * ------------ ----------------------------------------------------------
360 * d_fiq_nirq Source of the interrupt IRQ or FIQ.
361 *
362 * RETURN VALUE: None
363 *
364 ***************************************************************************/
365
366 #define F_INTH2_VALID_NEXT(d_fiq_nirq) * (volatile SYS_UWORD16 *) C_INTH2_CTRL_REG |= (1 << d_fiq_nirq)
367
368
369
370 /****************************************************************************
371 *
372 * MACRO NAME: F_INTH_GET_IRQ
373 * Return pending IRQ interrupt index on the main interrupt handler.
374 *
375 *
376 * ARGUMENT LIST:
377 *
378 * Argument Description
379 * ------------ ----------------------------------------------------------
380 *
381 * RETURN VALUE: IRQ interrupt index
382 *
383 ***************************************************************************/
384
385 #define F_INTH_GET_IRQ ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM)
386
387
388
389 /****************************************************************************
390 *
391 * MACRO NAME: F_INTH_GET_FIQ
392 * Return pending FIQ interrupt index on the main interrupt handler.
393 *
394 *
395 * ARGUMENT LIST:
396 *
397 * Argument Description
398 * ------------ ----------------------------------------------------------
399 *
400 * RETURN VALUE: FIQ interrupt index
401 *
402 ***************************************************************************/
403
404 #define F_INTH_GET_FIQ ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)
405
406
407
408 /****************************************************************************
409 *
410 * MACRO NAME: F_INTH2_GET_IRQ
411 * Return pending IRQ interrupt index on the 2nd level interrupt handler.
412 *
413 *
414 * ARGUMENT LIST:
415 *
416 * Argument Description
417 * ------------ ----------------------------------------------------------
418 *
419 * RETURN VALUE: FIQ interrupt index
420 *
421 ***************************************************************************/
422
423 #define F_INTH2_GET_IRQ ((* (SYS_UWORD16 *) C_INTH2_B_IRQ_REG) & C_INTH2_SRC_NUM)
424
425
426
427 /****************************************************************************
428 * STRUCTURE DEFINITION
429 ***************************************************************************/
430
431 typedef struct {
432 SYS_UWORD8 d_fiq_nirq;
433 SYS_UWORD8 d_edge_nlevel;
434 SYS_UWORD8 d_priority;
435 SYS_FUNC d_it_handler;
436 } T_INTH_CONFIG;
437
438
439
440 /****************************************************************************
441 * GLOBAL VARIABLES REFERENCE
442 ***************************************************************************/
443
444 extern SYS_FUNC a_inth_it_handlers[C_INTH_NUM_INT][2];
445 extern SYS_FUNC a_inth2_irq_handlers[C_INTH_2ND_NUM_INT];
446
447
448 /****************************************************************************
449 * PROTOTYPE DEFINITION
450 ***************************************************************************/
451
452 /*
453 * 16-BIS functions
454 */
455 extern void f_inth_setup(T_INTH_CONFIG *p_inth_config);
456 extern SYS_UWORD16 f_inth_get_version(void);
457
458 /*
459 * 32-BIS functions
460 */
461 extern void f_inth_dummy(void);
462 extern void f_inth_irq_handler(void);
463 extern void f_inth_fiq_handler(void);
464 extern void f_inth_2nd_level_handler(void);
465
466 #endif /* __SYS_INTH_H__ */
467
468 #endif /* (CHIPSET == 12) */