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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf12.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 #include "fc-target.cfg"
13
14 #define RF_RITA_10 0x2030 // Check with TIDK
15
16 //#define RF_HW_BAND_EGSM
17 //#define RF_HW_BAND_DCS
18 #define RF_HW_BAND_PCS 0x4
19 #define RF_HW_BAND_DUAL_US 0x80
20 #define RF_HW_BAND_DUAL_EXT 0x20
21
22 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
23 // radio_band_support E-GSM/DCS + GSM850/PCS
24 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US)
25
26 // L1 RF SW Multiband configuration
27 //--------------------------
28
29 // RF_SW_MULTIBAND_SUPPORT values
30 #define SINGLE_BAND_900 1
31 #define SINGLE_BAND_1800 2
32 #define SINGLE_BAND_850 3
33 #define SINGLE_BAND_1900 4
34 #define DUAL_BAND_900_1800 5
35 #define DUAL_BAND_850_1900 6
36 #define TRI_BAND_900_1800_1900 7
37 #define TRI_BAND_850_1900_1800 8
38 #define QUAD_BAND 9
39
40 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software
41 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1
42 // And also match the RF HW support: RF_HW_BAND_SUPPORT
43 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND
44
45 // Generate band dependancy options
46 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
47 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) )
48
49 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
50 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
51 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
52
53 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
54 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
55
56 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
57 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
58 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
59
60 /************************************/
61 /* SYNTHESIZER setup time... */
62 /************************************/
63 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
64 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
65
66 /************************************/
67 /* time for TPU scenario ending... */
68 /************************************/
69 //
70 // The following values are used to take into account any TPU activity AFTER
71 // BDLON (or BDLENA) down (for RX) and BULON down (for TX)
72 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down,
73 // these defines must be ZERO
74 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down,
75 // these defines must be equal to the time difference (in qbits) between
76 // the BDLON (or BDLENA) or BULON time and the last TPU command on
77 // the TPU scenario
78 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down
79 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down
80
81
82 /******************************************************/
83 /* TXPWR configuration... */
84 /* Fixed TXPWR value when GSM management is disabled. */
85 /******************************************************/
86
87 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
88 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
89 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
90 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
91 #endif
92
93
94 /************************************/
95 /* ANALOG delay (in qbits) */
96 /************************************/
97 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
98 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block
99 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
100 #if (ANLG_FAM == 1)
101 #define UL_ABB_DELAY 3 // modulator input to output delay
102 #endif
103 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
104 #define UL_ABB_DELAY 3 // modulator input to output delay
105 #endif
106
107 /************************************/
108 /* TX Propagation delay... */
109 /************************************/
110 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
111 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
112 #endif
113
114 /************************************/
115 /* Initial value for APC DELAY */
116 /************************************/
117 #if (ANLG_FAM == 1)
118 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
119 #define APCDEL_DOWN 2 // minimum value: 2
120 #define APCDEL_UP (6+5) // minimum value: 6
121 #endif
122
123 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
124 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
125 #define APCDEL_DOWN (2+0) // minimum value: 2
126 #define APCDEL_UP (6+3+1) // minimum value: 6
127 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8)
128 #endif
129
130 #define GUARD_BITS 7
131
132 /************************************/
133 /* Initial value for AFC... */
134 /************************************/
135 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
136
137 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames
138 // Rita (RF=12) LDO wakeup requires 6 frames
139
140 /************************************/
141 /* Baseband registers */
142 /************************************/
143 #if (ANLG_FAM == 1)
144 // Omega registers values will be programmed at 1st DSP communication interrupt
145 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
146 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
147 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute
148 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB
149 // RITA does not need an APCOFFSET because the PACTRL is internal:
150 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12
151 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
152 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
153 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
154 #define C_DAI_ON_OFF (0x000) // value at reset
155 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
156 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
157 // BULRUDEL will be initialized on rach only ....
158 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
159 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
160 #endif
161
162 #if (ANLG_FAM == 2)
163
164 // IOTA registers values will be programmed at 1st DSP communication interrupt
165
166 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
167 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
168 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3 dB, Sidetone gain to -17dB
169 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
170 // RITA does not need an APCOFFSET because the PACTRL is internal:
171 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128
172 #if (RF_PA == 0 || RF_PA == 3) || defined(CONFIG_TARGET_PIRELLI)
173 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
174 #elif defined(CONFIG_TARGET_COMPAL)
175 #define C_APCOFF ((0x060 << 6) | APCOFF | TRUE) // x2 slope 128
176 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
177 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
178 #endif
179 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
180 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
181 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
182 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
183
184
185 // audio patch for H2-sample:
186 #if (RAZ_VULSWITCH_REGAUDIO == 1)
187 #define C_VBCTRL1 ((0x003 << 6) | VBCTRL1 | TRUE) // VBDFAUXG = 1, VULSWITCH=0, VDLAUX=1, VDLEAR=1 // jkb h2sample change
188 #else
189 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
190 #endif
191
192
193 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE) // MICBIASEL=0, VDLHSO=0, MICAUX=0
194 // BULRUDEL will be initialized on rach only ....
195 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
196 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
197 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
198 // Monoslot, Vpp=8/15*Vref
199 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
200 #endif
201
202 #if (ANLG_FAM == 3)
203
204 // SYREN registers values will be programmed at 1st DSP communication interrupt
205
206 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
207 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
208 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3dB, Sidetone gain to -17 dB
209 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
210 #if (RF_PA == 0 || RF_PA == 3)
211 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
212 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
213 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
214 #endif
215 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
216 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
217 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
218 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
219 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE) // VULSWITCH=1 AUXI 28,2 dB
220 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE) // HSMIC on, SPKG gain @ 2,5dB
221
222 // BULRUDEL will be initialized on rach only ....
223 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
224 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
225 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
226 // Monoslot, Vpp=8/15*Vref
227 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
228
229 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE) // HSOAUTO enabled only
230 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
231 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE) // Init to zero
232 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE) // Speech on all outputs
233 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE) // Init to zero
234 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE) // Init to zero
235
236 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
237
238 #define C_BBCFG (0x44) // Syren Like BDLF Filter - DC OFFSET removal OFF
239
240 #endif
241
242
243 /************************************/
244 /* Automatic frequency compensation */
245 /************************************/
246 /********************* C_Psi_sta definition *****************************/
247 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
248 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
249 /* regarding Vega V/N = 2.4/4096 */
250 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
251 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
252 /* = 0.000195748 */
253 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
254 /************************************************************************/
255
256 #ifdef CONFIG_TARGET_PIRELLI
257
258 /* matching Pirelli's fw as read out via rftr 9 */
259 #define C_Psi_sta_inv 6974L // (1/C_Psi_sta)
260 #define C_Psi_st 8L // C_Psi_sta * 0.8 F0.16
261 #define C_Psi_st_32 492713L // F0.32
262 #define C_Psi_st_inv 8717L // (1/C_Psi_st)
263
264 #else
265
266 /* original TCS211 values */
267 #define C_Psi_sta_inv 5419L // (1/C_Psi_sta)
268 #define C_Psi_st 10L // C_Psi_sta * 0.8 F0.16
269 #define C_Psi_st_32 634112L // F0.32
270 #define C_Psi_st_inv 6773L // (1/C_Psi_st)
271
272 #endif
273
274 #if (VCXO_ALGO == 1)
275 // Linearity parameters
276
277 #ifdef CONFIG_TARGET_COMPAL
278 /* matching Compal's fw as read out via rftr 9 */
279 #define C_AFC_DAC_CENTER ((1000)*8)
280 #define C_AFC_DAC_MIN ((-500)*8)
281 #define C_AFC_DAC_MAX ((2500)*8)
282 #else
283 /* original TCS211 values */
284 #define C_AFC_DAC_CENTER ((111)*8)
285 #define C_AFC_DAC_MIN ((-1196)*8)
286 #define C_AFC_DAC_MAX ((1419)*8)
287 #endif
288
289 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
290 #endif
291
292 typedef struct
293 {
294 WORD16 eeprom_afc;
295 UWORD32 psi_sta_inv;
296 UWORD32 psi_st;
297 UWORD32 psi_st_32;
298 UWORD32 psi_st_inv;
299
300 #if (VCXO_ALGO)
301 // VCXO adjustment parameters
302 // Parameters used when assuming linearity
303 WORD16 dac_center;
304 WORD16 dac_min;
305 WORD16 dac_max;
306 WORD16 snr_thr;
307 #endif
308 }
309 T_AFC_PARAMS;
310
311 /************************************/
312 /* Swap IQ definitions... */
313 /************************************/
314 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
315 #if (RF_PG == R_PG_10)
316 // PG 1.0 -> 1 (Swap RX only)
317 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
318 #define SWAP_IQ_GSM 1
319 #define SWAP_IQ_DCS 1
320 #define SWAP_IQ_PCS 1
321 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900
322 #else
323 // All PG versions ABOVE 1.0 -> 0 (No Swap)
324 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
325 #define SWAP_IQ_GSM 0
326 #define SWAP_IQ_DCS 0
327 #define SWAP_IQ_PCS 0
328 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900
329 #endif
330
331 /************************************/
332 /************************************/
333 // typedef
334 /************************************/
335 /************************************/
336
337 /*************************************************************/
338 /* Define structure for apc of TX Power ******/
339 /*************************************************************/
340 typedef struct
341 { // pcm-file "rf/tx/level.gsm|dcs"
342 UWORD16 apc; // 0..31
343 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
344 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
345 }
346 T_TX_LEVEL;
347
348 /************************************/
349 /* Automatic Gain Control */
350 /************************************/
351 /* Define structure for sub-band definition of TX Power ******/
352 typedef struct
353 {
354 UWORD16 upper_bound; //highest physical arfcn of the sub-band
355 WORD16 agc_calib; // AGC for each TXPWR
356 }T_RF_AGC_BAND;
357
358 /************************************/
359 /* Ramp definitions */
360 /************************************/
361 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
362 typedef struct
363 {
364 UWORD8 ramp_up [16]; // Ramp-up profile
365 UWORD8 ramp_down [16]; // Ramp-down profile
366 }
367 T_TX_RAMP;
368 #endif
369
370
371 // RF structure definition
372 //========================
373
374 // Number of bands supported
375 #define GSM_BANDS 2
376
377 #define MULTI_BAND1 0
378 #define MULTI_BAND2 1
379 // RF table sizes
380 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
381 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
382
383 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
384 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
385 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
386 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
387 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
388
389 #define AGC_TABLE_SIZE 20
390 #define MIN_AGC_INDEX 6
391
392 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
393
394
395 // RX parameters and tables
396 //-------------------------
397
398 // AGC parameters and tables
399 typedef struct
400 {
401 UWORD16 low_agc_noise_thr;
402 UWORD16 high_agc_sat_thr;
403 UWORD16 low_agc;
404 UWORD16 high_agc;
405 UWORD8 il2agc_pwr[121];
406 UWORD8 il2agc_max[121];
407 UWORD8 il2agc_av[121];
408 }
409 T_AGC;
410
411 // Calibration parameters
412 typedef struct
413 {
414 UWORD16 g_magic;
415 UWORD16 lna_att;
416 UWORD16 lna_switch_thr_low;
417 UWORD16 lna_switch_thr_high;
418 }
419 T_RX_CAL_PARAMS;
420
421 // RX temperature compensation
422 typedef struct
423 {
424 WORD16 temperature;
425 WORD16 agc_calib;
426 }
427 T_RX_TEMP_COMP;
428
429 // RF RX structure
430 typedef struct
431 {
432 T_AGC agc;
433 }
434 T_RF_RX; //common
435
436 // RF RX structure
437 typedef struct
438 {
439 T_RX_CAL_PARAMS rx_cal_params;
440 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
441 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
442 }
443 T_RF_RX_BAND;
444
445
446 // TX parameters and tables
447 //-------------------------
448
449 // TX temperature compensation
450 typedef struct
451 {
452 WORD16 temperature;
453 #if (ORDER2_TX_TEMP_CAL==1)
454 WORD16 a;
455 WORD16 b;
456 WORD16 c;
457 #else
458 WORD16 apc_calib;
459 #endif
460 }
461 T_TX_TEMP_CAL;
462
463 // Ramp up and ramp down delay
464 typedef struct
465 {
466 UWORD16 up;
467 UWORD16 down;
468 }
469 T_RAMP_DELAY;
470
471 typedef struct
472 {
473 UWORD16 arfcn_limit;
474 WORD16 chan_cal;
475 }
476 T_TX_CHAN_CAL;
477
478 // RF TX structure
479 typedef struct
480 {
481 T_RAMP_DELAY ramp_delay;
482 UWORD8 guard_bits; // number of guard bits needed for ramp up
483 UWORD8 prg_tx;
484 }
485 T_RF_TX; //common
486
487 // RF TX structure
488 typedef struct
489 {
490 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
491 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
492 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
493 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
494 }
495 T_RF_TX_BAND;
496
497 // band structure
498 typedef struct
499 {
500 T_RF_RX_BAND rx;
501 T_RF_TX_BAND tx;
502 UWORD8 swap_iq;
503 }
504 T_RF_BAND;
505
506 // RF structure
507 typedef struct
508 {
509 // common for all bands
510 UWORD16 rf_revision;
511 UWORD16 radio_band_support;
512 T_RF_RX rx;
513 T_RF_TX tx;
514 T_AFC_PARAMS afc;
515 }
516 T_RF;
517
518 /************************************/
519 /* MADC definitions */
520 /************************************/
521 // Omega: 5 external channels if touch screen not used, 3 otherwise
522 enum ADC_INDEX {
523 ADC_VBAT,
524 ADC_VCHARG,
525 ADC_ICHARG,
526 ADC_VBACKUP,
527 ADC_BATTYP,
528 ADC_BATTEMP,
529 ADC_ADC3, // name of this ??
530 ADC_RFTEMP,
531 ADC_ADC4,
532 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
533 };
534
535 typedef struct
536 {
537 WORD16 converted[ADC_INDEX_END]; // converted
538 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
539 }
540 T_ADC;
541
542 /************************************/
543 /* MADC calibration */
544 /************************************/
545 typedef struct
546 {
547 UWORD16 a[ADC_INDEX_END];
548 WORD16 b[ADC_INDEX_END];
549 }
550 T_ADCCAL;
551
552 // Conversion table: ADC value -> temperature
553 typedef struct
554 {
555 UWORD16 adc; // ADC reading is 10 bits
556 WORD16 temp; // temp is in approx. range -30..+80
557 }
558 T_TEMP;
559
560 typedef struct
561 {
562 char *name;
563 void *addr;
564 int size;
565 }
566 T_CONFIG_FILE;
567
568 typedef struct
569 {
570 char *name; // name of ffs file suffix
571 T_RF_BAND *addr; // address to default flash structure
572 UWORD16 max_carrier; // max carrier
573 UWORD16 max_txpwr; // max tx power
574 }
575 T_BAND_CONFIG;
576
577 typedef struct
578 {
579 UWORD8 band[GSM_BANDS]; // index to band address
580 UWORD8 txpwr_tp; // tx power turning point
581 UWORD16 first_arfcn; // first index
582 }
583 T_STD_CONFIG;
584 enum GSMBAND_DEF
585 {
586 BAND_NONE,
587 BAND_EGSM900,
588 BAND_DCS1800,
589 BAND_PCS1900,
590 BAND_GSM850,
591 // put new bands here
592 BAND_GSM900 //last entry
593 };
594
595 /************************************/
596 /* ABB (Omega) Initialization */
597 /************************************/
598
599 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
600 #define ABB_TABLE_SIZE 16
601 #elif (ANLG_FAM == 3)
602 #define ABB_TABLE_SIZE 22
603 #endif
604
605 // Note that this translation is probably not needed at all. But until L1 is
606 // (maybe) changed to simply initialize the ABB from a table of words, we
607 // use this to make things more easy-readable.
608
609 #if (ANLG_FAM == 1)
610 enum ABB_REGISTERS {
611 ABB_AFCCTLADD = 0,
612 ABB_VBUCTRL,
613 ABB_VBDCTRL,
614 ABB_BBCTRL,
615 ABB_APCOFF,
616 ABB_BULIOFF,
617 ABB_BULQOFF,
618 ABB_DAI_ON_OFF,
619 ABB_AUXDAC,
620 ABB_VBCTRL,
621 ABB_APCDEL1
622 };
623 #elif (ANLG_FAM == 2)
624 enum ABB_REGISTERS {
625 ABB_AFCCTLADD = 0,
626 ABB_VBUCTRL,
627 ABB_VBDCTRL,
628 ABB_BBCTRL,
629 ABB_BULGCAL,
630 ABB_APCOFF,
631 ABB_BULIOFF,
632 ABB_BULQOFF,
633 ABB_DAI_ON_OFF,
634 ABB_AUXDAC,
635 ABB_VBCTRL1,
636 ABB_VBCTRL2,
637 ABB_APCDEL1,
638 ABB_APCDEL2
639 };
640 #elif (ANLG_FAM == 3)
641 enum ABB_REGISTERS {
642 ABB_AFCCTLADD = 0,
643 ABB_VBUCTRL,
644 ABB_VBDCTRL,
645 ABB_BBCTRL,
646 ABB_BULGCAL,
647 ABB_APCOFF,
648 ABB_BULIOFF,
649 ABB_BULQOFF,
650 ABB_DAI_ON_OFF,
651 ABB_AUXDAC,
652 ABB_VBCTRL1,
653 ABB_VBCTRL2,
654 ABB_APCDEL1,
655 ABB_APCDEL2,
656 ABB_VBPOP,
657 ABB_VAUDINITD,
658 ABB_VAUDCTRL,
659 ABB_VAUOCTRL,
660 ABB_VAUSCTRL,
661 ABB_VAUDPLL
662 };
663 #endif
664 #endif