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comparison src/cs/layer1/include/l1_const.h @ 0:b6a5e36de839

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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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children 0d96c28dedb1
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-1:000000000000 0:b6a5e36de839
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_CONST.H
4 *
5 * Filename l1_const.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifdef __MSDOS__ // Running BORLANDC compiler.
11 #ifdef MVC
12 #define EXIT exit(0)
13 #define FAR
14 #else
15 #define EXIT DOS_Exit(0)
16 #define FAR far
17 #endif
18 #else // Running ARM compiler.
19 #define FAR
20 #define EXIT exit(0)
21 #define stricmp strcmp
22 #endif
23
24
25 #if (CODE_VERSION != SIMULATION)
26 #define NULL 0
27 #endif
28
29 #define NO_PAR 0
30
31 #define NO_TASK 0
32 #define ALL_TASK 0xffffffff
33 #define ALL_PARAM 0xffffffff
34
35 #define TRUE 1
36 #define TRUE_L 1L
37 #define FALSE 0
38
39 #define NOT_PENDING 0
40 #define PENDING 1
41
42 #define INACTIVE 2
43 #define ACTIVE 3
44 #define RE_ENTERED 4
45 #define WAIT_IQ 5
46
47 //---------------------------------------------
48 // MCU-DSP bit-field bit position definitions
49 //---------------------------------------------
50 #if L1_GPRS
51 #define GPRS_SCHEDULER 1 // Select GPRS scheduler
52 #endif
53 #define GSM_SCHEDULER 2 // Select GSM scheduler
54
55 //-----------------------------
56 // POWER MANAGEMENT............
57 //-----------------------------
58 #define MIN_SLEEP_TIME (SETUP_FRAME+2+l1_config.params.setup_afc_and_rf) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(2)
59 #define TPU_LOAD 01
60 #define TPU_FREEZE 02
61
62 // SLEEP ALGO SWITCH
63 #define NO_SLEEP 00 // ------ + ------ + ------
64 #define SMALL_SLEEP 01 // SMALL + ------ + ------
65 #define BIG_SLEEP 02 // ------ + BIG + ------
66 #define DEEP_SLEEP 03 // ------ + BIG + DEEP
67 #define ALL_SLEEP 04 // SMALL + BIG + DEEP
68
69 // GAUGING SAMPLES
70 #define SIZE_HIST 10
71 #define MAX_BAD_GAUGING 3
72
73 // GAUG_IN_32T = (HF in clock of 13Mhz*dpll) * ( LF in Khz)
74 #define GAUG_IN_32T 1348 // gauging duration is 1348*T32 measured on eva4
75
76 // DSP state need to be used to enter Deep Sleep mode
77 #if (W_A_DSP_IDLE3 == 1)
78 #define C_DSP_IDLE3 3
79 #endif
80
81 //-------------------------------------------------
82 // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
83 // to face temperature variation
84 //
85 // ACQUIS: variations allowed 32.768Khz +- 50 ppm
86 // 9 frames gauging is 1348*T32 (measured on eva4)
87 // UPDATE: variation allowed is +- 6 ppm jitter
88 //-------------------------------------------------
89
90 #define MCUCLK 13000 // 13 Mhz
91 #define LF 32.768
92 #define LF_100PPM 32.7712768 // 32.768*(1+100*10E-6)
93 #define LF_500PPM 32.751616 // 32.768*(1-500*10E-6)
94 #define LF_50PPM 32.7696384 // 32.768*(1+50*10E-6)
95 #define LF_6PPM 32.76819661 // 32.768*(1+6*10E-6)
96
97 #define NB_INIT 5 // nbr of gauging to pass to ACQUIS
98 #define NB_ACQU 10 // nbr of gauging to pass to UPDATE
99
100 #if (CHIPSET ==2 || CHIPSET ==3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9) // PLL is at 65 Mhz !!!!!!
101 #define PLL 5 // 5*13Mhz = 65 Mhz
102 //-------------------------------------------------
103 // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
104 //
105 // ACQUIS: variations allowed 32.768Khz +- 50 ppm
106 // 9 frames gauging is 1348*T32 (measured on eva4)
107 // UPDATE: variation allowed is +- 6 ppm jitter
108 //-------------------------------------------------
109 #define C_CLK_MIN 1983 // 65000/32.7712768 = 1983.444234
110 #define C_CLK_INIT_MIN 29113 // 0.444234*2^16
111 #define C_CLK_MAX 1984 // 65000 / 32.751616 = 1984.634896
112 #define C_CLK_INIT_MAX 41608 // 0.634896*2^16
113 #define C_DELTA_HF_ACQUIS 130 // 1348/32.768-1348/32.7696384 = 0.002056632ms
114 // 0.002056632/0.0001538 = 130 T65Mhz
115 #define C_DELTA_HF_UPDATE 15 // 1348/32.768-1348/32.76819661 =0.00024691ms
116 // 0.00024691/0.0001538 = 15 T65Mhz
117 #endif
118
119 #define ARMIO_CLK_CUT 0x0001
120 #define UWIRE_CLK_CUT 0x0002
121
122 //-----------------------------
123 // Neighbour cell sync. reading
124 //-----------------------------
125 #if (L1_12NEIGH)
126 #define NBR_NEIGHBOURS 12
127 #else
128 #define NBR_NEIGHBOURS 6
129 #endif
130
131 //-----------------------------
132 // LAYER 1 MEASUREMENT TASKS...
133 //-----------------------------
134 #define NBR_L1S_MEAS_TASKS 4
135
136 #define FSMS 0
137 #define I_BAMS 1
138 #define D_BAMS 2
139 #define SERVMS 3
140
141 #define FSMS_MEAS (TRUE_L << FSMS) // Measurement task on FULL list (Cell Selection/Idle).
142 #define I_BAMS_MEAS (TRUE_L << I_BAMS) // Measurement task on BA list in Idle.
143 #define D_BAMS_MEAS (TRUE_L << D_BAMS) // Measurement task on BA list in Dedicated.
144 #define SERVMS_MEAS (TRUE_L << SERVMS) // Measurement task for Serving.
145
146 #define FSMS_MEAS_MASK ALL_TASK ^ FSMS_MEAS
147 #define I_BAMS_MEAS_MASK ALL_TASK ^ I_BAMS_MEAS
148 #define D_BAMS_MEAS_MASK ALL_TASK ^ D_BAMS_MEAS
149 #define SERVMS_MEAS_MASK ALL_TASK ^ SERVMS_MEAS
150
151 #define A_D_BLEN 456 // SACCH/SDCCH data block length (GSM 5.01 $7)
152 #define TCH_FS_BLEN 378 // TCH FULL SPEECH block length
153 #define TCH_HS_BLEN 211 // TCH HALF SPEECH block length
154 #define TCH_F_D_BLEN 456 // FACCH, TCH_DATA block length
155
156 /*
157 * FreeCalypso Frankenstein: the following definition was not present in
158 * our TCS211 version and we had to pull it from the LoCosto version for
159 * l1_cmplx.c to compile. However, the comment in the place where it is
160 * used says that it "valuable for code running on target with DSP 3606."
161 */
162 #define MIN_ACCEPTABLE_SNR_FOR_SB 200 // threshold under which a SB shall be considered as not found
163
164 // Define max PM/TDMA according to DSP code and TPU RAM size
165 //----------------------------------------------------------
166
167 // NOTE: we should use a global variable initialized at L1 start and function of rx synth setup time.
168
169 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 4))
170
171 // TPU RAM size limitation
172
173 #define NB_MEAS_MAX 4
174 #define NB_MEAS_MAX_GPRS 4
175
176 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
177
178 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
179
180 // DSP code 33: upto 8 PMs with GSM and GPRS scheduler
181
182 #define NB_MEAS_MAX 8
183 #define NB_MEAS_MAX_GPRS 8
184
185 #elif (DSP == 32)
186
187 // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
188 // and 8 PMs with GPRS scheduler, 6 for DSP 32 because of CPU load
189
190 #define NB_MEAS_MAX 4
191 #define NB_MEAS_MAX_GPRS 6
192
193 #else
194
195
196 // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
197 // and 8 PMs with GPRS scheduler
198
199 #define NB_MEAS_MAX 4
200 #define NB_MEAS_MAX_GPRS 8
201
202 #endif
203 #endif
204 #if (AMR == 1)
205 #define SID_UPDATE_BLEN 212 // SID UPDATE block length
206 #define RATSCCH_BLEN 212 // RATSCCH block length
207 #define TCH_AFS_BLEN 448 // TCH Adaptative Full rate Speech block length
208 // Note: the d_nerr value is calculated thanks to the bit class 1 of the block.
209 // But the number AHS bit class 1 depends on the type of vocoder currently used (c.f. 5.03 &3.10.7.2)
210 #define TCH_AHS_7_95_BLEN 188 // TCH AHS 7.95 Speech block length
211 #define TCH_AHS_7_4_BLEN 196 // TCH AHS 7.4 Speech block length
212 #define TCH_AHS_6_7_BLEN 200 // TCH AHS 6.7 Speech block length
213 #define TCH_AHS_5_9_BLEN 208 // TCH AHS 5.9 Speech block length
214 #define TCH_AHS_5_15_BLEN 212 // TCH AHS 5.15 Speech block length
215 #define TCH_AHS_4_75_BLEN 212 // TCH AHS 4.75 Speech block length
216 #endif
217 //----------------------------------------
218 // LAYER 1 Asynchronous processes names...
219 //----------------------------------------
220 #if (TESTMODE) && !(L1_GPRS)
221 #if (AUDIO_TASK == 1)
222 #if (L1_GTT)
223 #if (OP_L1_STANDALONE == 1)
224 #define NBR_L1A_PROCESSES 45
225 #else
226 #define NBR_L1A_PROCESSES 44
227 #endif
228 #else
229 #if (OP_L1_STANDALONE == 1)
230 #define NBR_L1A_PROCESSES 44
231 #else
232 #define NBR_L1A_PROCESSES 43
233 #endif
234 #endif
235 #else
236 #if (L1_GTT)
237 #if (OP_L1_STANDALONE == 1)
238 #define NBR_L1A_PROCESSES 27
239 #else
240 #define NBR_L1A_PROCESSES 26
241 #endif
242 #else
243 #if (OP_L1_STANDALONE == 1)
244 #define NBR_L1A_PROCESSES 26
245 #else
246 #define NBR_L1A_PROCESSES 25
247 #endif
248 #endif
249 #endif
250 #endif
251
252 #if (TESTMODE) && (L1_GPRS)
253 #if (AUDIO_TASK == 1)
254 #if (L1_GTT)
255 #if (OP_L1_STANDALONE == 1)
256 #define NBR_L1A_PROCESSES 46
257 #else
258 #define NBR_L1A_PROCESSES 45
259 #endif
260 #else
261 #if (OP_L1_STANDALONE == 1)
262 #define NBR_L1A_PROCESSES 45
263 #else
264 #define NBR_L1A_PROCESSES 44
265 #endif
266 #endif
267 #else
268 #if (L1_GTT)
269 #if (OP_L1_STANDALONE == 1)
270 #define NBR_L1A_PROCESSES 28
271 #else
272 #define NBR_L1A_PROCESSES 27
273 #endif
274 #else
275 #if (OP_L1_STANDALONE == 1)
276 #define NBR_L1A_PROCESSES 27
277 #else
278 #define NBR_L1A_PROCESSES 26
279 #endif
280 #endif
281 #endif
282 #endif
283
284 #if !(TESTMODE)
285 #if (AUDIO_TASK == 1)
286 #if (L1_GTT)
287 #if (OP_L1_STANDALONE == 1)
288 #define NBR_L1A_PROCESSES 37
289 #else
290 #define NBR_L1A_PROCESSES 36
291 #endif
292 #else
293 #if (OP_L1_STANDALONE == 1)
294 #define NBR_L1A_PROCESSES 36
295 #else
296 #define NBR_L1A_PROCESSES 35
297 #endif
298 #endif
299 #else
300 #if (L1_GTT)
301 #if (OP_L1_STANDALONE == 1)
302 #define NBR_L1A_PROCESSES 19
303 #else
304 #define NBR_L1A_PROCESSES 18
305 #endif
306 #else
307 #if (OP_L1_STANDALONE == 1)
308 #define NBR_L1A_PROCESSES 18
309 #else
310 #define NBR_L1A_PROCESSES 17
311 #endif
312 #endif
313 #endif
314 #endif
315
316
317 #define FULL_MEAS 0 // l1a_full_list_meas_process(msg)
318 #define CS_NORM 1 // l1a_cs_bcch_process(msg)
319 #define I_6MP 2 // l1a_idle_6strongest_monitoring_process(msg)
320 #define I_SCP 3 // l1a_idle_serving_cell_paging_process(msg)
321 #define I_SCB 4 // l1a_idle_serving_cell_bcch_reading_process(msg)
322 #define I_SMSCB 5 // l1a_idle_smscb_process(msg)
323 #define CR_B 6 // l1a_cres_process(msg)
324 #define ACCESS 7 // l1a_access_process(msg)
325 #define DEDICATED 8 // l1a_dedicated_process(msg)
326 #define I_FULL_MEAS 9 // l1a_dedicated_process(msg)
327 #define I_NMEAS 10 // l1a_idle_ba_meas_process(msg)
328 #define DEDIC_6 11 // l1a_dedic6_process(msg)
329 #define D_NMEAS 12 // l1a_dedic_ba_list_meas_process(msg)
330 #define HW_TEST 13 // l1a_test_process(msg)
331 #define I_BCCHN 14 // l1a_idle_neighbour_cell_bcch_reading_process(msg)
332 #define I_ADC 15 // l1a_mmi_adc_req(msg)
333
334 #if (TESTMODE) && !(L1_GPRS)
335 #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
336 #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
337 #define TMODE_SB 18 // l1a_tmode_sb_process(msg)
338 #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
339 #define TMODE_RA 20 // l1a_tmode_access_process(msg)
340 #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
341 #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
342 #define TMODE_PM 23 // l1a_tmode_meas_process(msg)
343 #if (AUDIO_TASK == 1)
344 #define L1A_KEYBEEP_STATE 24 // l1a_mmi_keybeep_process(msg)
345 #define L1A_TONE_STATE 25 // l1a_mmi_tone_process(msg)
346 #define L1A_MELODY0_STATE 26 // l1a_mmi_melody0_process(msg)
347 #define L1A_MELODY1_STATE 27 // l1a_mmi_melody1_process(msg)
348 #define L1A_VM_PLAY_STATE 28 // l1a_mmi_vm_playing_process(msg)
349 #define L1A_VM_RECORD_STATE 29 // l1a_mmi_vm_recording_process(msg)
350 #define L1A_SR_ENROLL_STATE 30 // l1a_mmi_sr_enroll_process(msg)
351 #define L1A_SR_UPDATE_STATE 31 // l1a_mmi_sr_update_process(msg)
352 #define L1A_SR_RECO_STATE 32 // l1a_mmi_sr_reco_process(msg)
353 #define L1A_SR_UPDATE_CHECK_STATE 33 // l1a_mmi_sr_update_check_process(msg)
354 #define L1A_AEC_STATE 34 // l1a_mmi_aec_process(msg)
355 #define L1A_FIR_STATE 35 // l1a_mmi_fir_process(msg)
356 #define L1A_AUDIO_MODE_STATE 36 // l1a_mmi_audio_mode_process(msg)
357 #define L1A_MELODY0_E2_STATE 37 // l1a_mmi_melody0_e2_process(msg)
358 #define L1A_MELODY1_E2_STATE 38 // l1a_mmi_melody1_e2_process(msg)
359 #define L1A_VM_AMR_PLAY_STATE 39 // l1a_mmi_vm_amr_playing_process(msg)
360 #define L1A_VM_AMR_RECORD_STATE 40 // l1a_mmi_vm_amr_recording_process(msg)
361 #define L1A_CPORT_STATE 41 // l1a_mmi_cport_process(msg)
362 #if (L1_GTT == 1)
363 #define L1A_GTT_STATE 42 // l1a_mmi_gtt_process(msg)
364 #define INIT_L1 43 // l1a_init_layer1_process(msg)
365 #if (OP_L1_STANDALONE == 1)
366 #define HSW_CONF 44 // l1a_test_config_process(msg)
367 #endif
368 #else
369 #define INIT_L1 42 // l1a_init_layer1_process(msg)
370 #if (OP_L1_STANDALONE == 1)
371 #define HSW_CONF 43 // l1a_test_config_process(msg)
372 #endif
373 #endif
374 #else
375 #if (L1_GTT == 1)
376 #define L1A_GTT_STATE 24 // l1a_mmi_gtt_process(msg)
377 #define INIT_L1 25 // l1a_init_layer1_process(msg)
378 #if (OP_L1_STANDALONE == 1)
379 #define HSW_CONF 26 // l1a_test_config_process(msg)
380 #endif
381 #else
382 #define INIT_L1 24 // l1a_init_layer1_process(msg)
383 #if (OP_L1_STANDALONE == 1)
384 #define HSW_CONF 25 // l1a_test_config_process(msg)
385 #endif
386 #endif
387 #endif
388 #endif
389
390 #if (TESTMODE) && (L1_GPRS)
391 #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
392 #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
393 #define TMODE_SB 18 // l1a_tmode_sb_process(msg)
394 #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
395 #define TMODE_RA 20 // l1a_tmode_access_process(msg)
396 #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
397 #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
398 #define TMODE_PM 23 // l1a_tmode_meas_process(msg)
399 #define TMODE_TRANSFER 24 // l1a_tmode_transfer_process(msg)
400 #if (AUDIO_TASK == 1)
401 #define L1A_KEYBEEP_STATE 25 // l1a_mmi_keybeep_process(msg)
402 #define L1A_TONE_STATE 26 // l1a_mmi_tone_process(msg)
403 #define L1A_MELODY0_STATE 27 // l1a_mmi_melody0_process(msg)
404 #define L1A_MELODY1_STATE 28 // l1a_mmi_melody1_process(msg)
405 #define L1A_VM_PLAY_STATE 29 // l1a_mmi_vm_playing_process(msg)
406 #define L1A_VM_RECORD_STATE 30 // l1a_mmi_vm_recording_process(msg)
407 #define L1A_SR_ENROLL_STATE 31 // l1a_mmi_sr_enroll_process(msg)
408 #define L1A_SR_UPDATE_STATE 32 // l1a_mmi_sr_update_process(msg)
409 #define L1A_SR_RECO_STATE 33 // l1a_mmi_sr_reco_process(msg)
410 #define L1A_SR_UPDATE_CHECK_STATE 34 // l1a_mmi_sr_update_check_process(msg)
411 #define L1A_AEC_STATE 35 // l1a_mmi_aec_process(msg)
412 #define L1A_FIR_STATE 36 // l1a_mmi_fir_process(msg)
413 #define L1A_AUDIO_MODE_STATE 37 // l1a_mmi_audio_mode_process(msg)
414 #define L1A_MELODY0_E2_STATE 38 // l1a_mmi_melody0_e2_process(msg)
415 #define L1A_MELODY1_E2_STATE 39 // l1a_mmi_melody1_e2_process(msg)
416 #define L1A_VM_AMR_PLAY_STATE 40 // l1a_mmi_vm_amr_playing_process(msg)
417 #define L1A_VM_AMR_RECORD_STATE 41 // l1a_mmi_vm_amr_recording_process(msg)
418 #define L1A_CPORT_STATE 42 // l1a_mmi_cport_process(msg)
419 #if (L1_GTT == 1)
420 #define L1A_GTT_STATE 43
421 #define INIT_L1 44 // l1a_init_layer1_process(msg)
422 #if (OP_L1_STANDALONE == 1)
423 #define HSW_CONF 45 // l1a_test_config_process(msg)
424 #endif
425 #else
426 #define INIT_L1 43 // l1a_init_layer1_process(msg)
427 #if (OP_L1_STANDALONE == 1)
428 #define HSW_CONF 44 // l1a_test_config_process(msg)
429 #endif
430 #endif
431 #else
432 #if (L1_GTT == 1)
433 #define L1A_GTT_STATE 25
434 #define INIT_L1 26 // l1a_init_layer1_process(msg)
435 #if (OP_L1_STANDALONE == 1)
436 #define HSW_CONF 27 // l1a_test_config_process(msg)
437 #endif
438 #else
439 #define INIT_L1 25 // l1a_init_layer1_process(msg)
440 #if (OP_L1_STANDALONE == 1)
441 #define HSW_CONF 26 // l1a_test_config_process(msg)
442 #endif
443 #endif
444 #endif
445 #endif
446
447 #if !(TESTMODE) && (AUDIO_TASK == 1)
448 #define L1A_KEYBEEP_STATE 16 // l1a_mmi_keybeep_process(msg)
449 #define L1A_TONE_STATE 17 // l1a_mmi_tone_process(msg)
450 #define L1A_MELODY0_STATE 18 // l1a_mmi_melody0_process(msg)
451 #define L1A_MELODY1_STATE 19 // l1a_mmi_melody1_process(msg)
452 #define L1A_VM_PLAY_STATE 20 // l1a_mmi_vm_playing_process(msg)
453 #define L1A_VM_RECORD_STATE 21 // l1a_mmi_vm_recording_process(msg)
454 #define L1A_SR_ENROLL_STATE 22 // l1a_mmi_sr_enroll_process(msg)
455 #define L1A_SR_UPDATE_STATE 23 // l1a_mmi_sr_update_process(msg)
456 #define L1A_SR_RECO_STATE 24 // l1a_mmi_sr_reco_process(msg)
457 #define L1A_SR_UPDATE_CHECK_STATE 25 // l1a_mmi_sr_update_check_process(msg)
458 #define L1A_AEC_STATE 26 // l1a_mmi_aec_process(msg)
459 #define L1A_FIR_STATE 27 // l1a_mmi_fir_process(msg)
460 #define L1A_AUDIO_MODE_STATE 28 // l1a_mmi_audio_mode_process(msg)
461 #define L1A_MELODY0_E2_STATE 29 // l1a_mmi_melody0_e2_process(msg)
462 #define L1A_MELODY1_E2_STATE 30 // l1a_mmi_melody1_e2_process(msg)
463 #define L1A_VM_AMR_PLAY_STATE 31 // l1a_mmi_vm_amr_playing_process(msg)
464 #define L1A_VM_AMR_RECORD_STATE 32 // l1a_mmi_vm_amr_recording_process(msg)
465 #define L1A_CPORT_STATE 33 // l1a_mmi_cport_process(msg)
466 #if (L1_GTT == 1)
467 #define L1A_GTT_STATE 34 // l1a_mmi_tty_process(msg)
468 #define INIT_L1 35 // l1a_init_layer1_process(msg)
469 #if (OP_L1_STANDALONE == 1)
470 #define HSW_CONF 36 // l1a_test_config_process(msg)
471 #endif
472 #else
473 #define INIT_L1 34 // l1a_init_layer1_process(msg)
474 #if (OP_L1_STANDALONE == 1)
475 #define HSW_CONF 35 // l1a_test_config_process(msg)
476 #endif
477 #endif
478 #elif !(TESTMODE) && !(AUDIO_TASK == 1)
479 #if (L1_GTT == 1)
480 #define L1A_GTT_STATE 16 // l1a_mmi_tty_process(msg)
481 #define INIT_L1 17 // l1a_init_layer1_process(msg)
482 #if (OP_L1_STANDALONE == 1)
483 #define HSW_CONF 18 // l1a_test_config_process(msg)
484 #endif
485 #else
486 #define INIT_L1 16 // l1a_init_layer1_process(msg)
487 #if (OP_L1_STANDALONE == 1)
488 #define HSW_CONF 17 // l1a_test_config_process(msg)
489 #endif
490 #endif
491 #endif
492
493 #if TESTMODE
494 #define TMODE_UPLINK (1<<0)
495 #define TMODE_DOWNLINK (1<<1)
496 #endif
497
498 //------------------------------------
499 // LAYER 1 DOWNLINK & UPLINK TASKS...
500 //------------------------------------
501 #define TASK_DISABLED 0
502 #define TASK_ENABLED 1
503
504 #define SEMAPHORE_RESET 0
505 #define SEMAPHORE_SET 1
506
507 #define NO_NEW_TASK -1
508
509
510 // Tasks in the order of their priority (low to high).
511
512 #if !L1_GPRS
513
514 #define NBR_DL_L1S_TASKS 32
515
516 //GSM_TASKS/
517 #define HWTEST 0 // DSP checksum reading
518 #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
519 #define DEDIC 2 // Global Dedicated mode switch
520 #define RAACC 3 // Channel access (ul)
521 #define RAHO 4 // Handover access (ul)
522 #define NSYNC 5 // Global Neighbour cell synchro switch
523 #define FBNEW 6 // Frequency burst search (Idle mode)
524 #define SBCONF 7 // Synchro. burst confirmation
525 #define SB2 8 // Synchro. burst read (1 frame uncertainty / SB position)
526 #define FB26 9 // Frequency burst search, dedic/transfer mode MF26 or MF52
527 #define SB26 10 // Synchro burst search, dedic/transfer mode MF26 or MF52
528 #define SBCNF26 11 // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
529 #define FB51 12 // Frequency burst search, dedic mode MF51
530 #define SB51 13 // Synchro burst search, dedic MF51
531 #define SBCNF51 14 // Synchro burst confirmation, dedic MF51
532 #define BCCHN 15 // BCCH Neighbor in GSM Idle
533 #define ALLC 16 // All CCCH Reading
534 #define EBCCHS 17 // Extended BCCH Serving Reading
535 #define NBCCHS 18 // Normal BCCH ServingReading
536 #define SMSCB 19 // CBCH serving Reading
537 #define NP 20 // Normal paging Reading
538 #define EP 21 // Extended pagingReading
539 #define ADL 22 // SACCH(SDCCH) DL
540 #define AUL 23 // SACCH(SDCCH) UL
541 #define DDL 24 // SDCCH DL
542 #define DUL 25 // SDCCH UL
543 #define TCHD 26 // Dummy for TCH Half rate
544 #define TCHA 27 // SACCH(TCH)
545 #define TCHTF 28 // TCH Full rate
546 #define TCHTH 29 // TCH Half rate
547 #define BCCHN_TOP 30 // BCCH Neighbour TOP priority in Idle mode
548 #define SYNCHRO 31 // synchro task: L1S reset
549 //END_GSM_TASKS/
550
551 #else
552
553 #define NBR_DL_L1S_TASKS 45
554
555 //GPRS_TASKS/
556 #define HWTEST 0 // DSP checksum reading
557 #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
558 #define DEDIC 2 // Global Dedicated mode switch
559 #define RAACC 3 // Channel access (ul)
560 #define RAHO 4 // Handover access (ul)
561 #define NSYNC 5 // Global Neighbour cell synchro switch
562 #define POLL 6 // Packet Polling (Access)
563 #define PRACH 7 // Packet Random Access Channel
564 #define ITMEAS 8 // Interference measurements
565 #define FBNEW 9 // Frequency burst search (Idle mode)
566 #define SBCONF 10 // Synchro. burst confirmation
567 #define SB2 11 // Synchro. burst read (1 frame uncertainty / SB position)
568 #define PTCCH 12 // Packet Timing Advance control channel
569 #define FB26 13 // Frequency burst search, dedic/transfer mode MF26 or MF52
570 #define SB26 14 // Synchro burst search, dedic/transfer mode MF26 or MF52
571 #define SBCNF26 15 // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
572 #define FB51 16 // Frequency burst search, dedic mode MF51
573 #define SB51 17 // Synchro burst search, dedic MF51
574 #define SBCNF51 18 // Synchro burst confirmation, dedic MF51
575 #define PDTCH 19 // Packet Data channel
576 #define BCCHN 20 // BCCH Neighbor in GSM Idle
577 #define ALLC 21 // All CCCH Reading
578 #define EBCCHS 22 // Extended BCCH Serving Reading
579 #define NBCCHS 23 // Normal BCCH Serving Reading
580 #define ADL 24 // SACCH(SDCCH) DL
581 #define AUL 25 // SACCH(SDCCH) UL
582 #define DDL 26 // SDCCH DL
583 #define DUL 27 // SDCCH UL
584 #define TCHD 28 // Dummy for TCH Half rate
585 #define TCHA 29 // SACCH(TCH)
586 #define TCHTF 30 // TCH Full rate
587 #define TCHTH 31 // TCH Half rate
588 #define PALLC 32 // All PCCCH reading
589 #define SMSCB 33 // CBCH serving Reading
590 #define PBCCHS 34 // PBCCH serving reading
591 #define PNP 35 // Packet Normal paging Reading
592 #define PEP 36 // Packet Extended paging Reading
593 #define SINGLE 37 // Single Block for GPRS
594 #define PBCCHN_TRAN 38 // Packet BCCH Neighbor in Packet Transfer mode.
595 #define PBCCHN_IDLE 39 // Packet BCCH Neighbor in Idle mode.
596 #define BCCHN_TRAN 40 // BCCH Neighbour in Packet Transfer mode
597 #define NP 41 // Normal paging Reading
598 #define EP 42 // Extended paging Reading
599 #define BCCHN_TOP 43 // BCCH Neighbour TOP priority in Idle mode
600 #define SYNCHRO 44 // synchro task: L1S reset
601 //END_GPRS_TASKS/
602
603 #endif
604
605 //------------------------------------
606 // LAYER 1 API
607 //------------------------------------
608 #define MCSI_PORT1 0
609 #define MCSI_PORT2 1
610
611
612 //---------------------------------
613 // DSP vocoder Enable/ Disable
614 //---------------------------------
615
616 #if (L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
617 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
618 #define TCH_VOCODER_DISABLE_REQ 0
619 #define TCH_VOCODER_ENABLE_REQ 1
620 #define TCH_VOCODER_ENABLED 2
621 #define TCH_VOCODER_DISABLED 3
622
623 // Number of TDMA wait frames until the DSP output is steady
624 #define DSP_VOCODER_ON_TRANSITION 165
625 #endif // FF_L1_TCH_VOCODER_CONTROL
626 #endif
627
628 //---------------------------------
629 // Handover Finished cause defines.
630 //---------------------------------
631 #define HO_COMPLETE 0
632 #define HO_TIMEOUT 1
633
634 //---------------------------------
635 // FB detection algorithm defines.
636 //---------------------------------
637 #define FB_MODE_0 0 // FB detec. mode 0.
638 #define FB_MODE_1 1 // FB detec. mode 1.
639
640 //---------------------------------
641 // AFC control defines.
642 //---------------------------------
643 #define AFC_INIT 1
644 #define AFC_OPEN_LOOP 2
645 #define AFC_CLOSED_LOOP 3
646
647 // For VCXO algo.
648 #if (VCXO_ALGO)
649 #define AFC_INIT_CENTER 4
650 #define AFC_INIT_MAX 5
651 #define AFC_INIT_MIN 6
652 #endif
653 //---------------------------------
654 // TOA control defines.
655 //---------------------------------
656 #define TOA_INIT 1
657 #define TOA_RUN 2
658
659 //---------------------------------
660 // Neighbour Synchro possible status.
661 //---------------------------------
662 #define NSYNC_FREE 0
663 #define NSYNC_PENDING 1
664 #define NSYNC_COMPLETED 2
665 #if (L1_12NEIGH ==1)
666 #define NSYNC_WAIT 3
667 #endif
668
669 /************************************/
670 /* Layer 1 constants declaration... */
671 /************************************/
672 #define MAX_FN ((UWORD32)26*51*2048)
673
674 #if L1_GPRS
675 #define MAX_BLOCK_ID ((UWORD32) (3 * (UWORD32) (MAX_FN / 13))) // Block ID corresponding to fn = FN MAX
676 #endif
677
678 //--------------------------------------------------------
679 // standard specific constants used in l1_config.std.xxx
680 //--------------------------------------------------------
681
682
683 // GSM
684 #define FIRST_ARFCN_GSM 1 // 1st arfcn is 1
685 #define NBMAX_CARRIER_GSM 124 // 124 for GSM, 174 for E_GSM, 374 for DCS1800.
686 #define MAX_TXPWR_GSM 19 // lowest power ctrl level value in GSM band
687 // GSM_E
688 #define FIRST_ARFCN_EGSM 1 // 1st arfcn is 1
689 #define NBMAX_CARRIER_EGSM 174 // 174 carriers for GSM_E.
690 #define MAX_TXPWR_EGSM 19 // lowest power ctrl level value in GSM-E band
691 // PCS1900
692 #define FIRST_ARFCN_PCS 512 // 1st arfcn is 512
693 #define NBMAX_CARRIER_PCS 299 // 299 carriers for PCS1900.
694 #define MAX_TXPWR_PCS 15 // lowest power ctrl level value in PCS band
695 #define TXPWR_TURNING_POINT_PCS 21
696 // DCS1800
697 #define FIRST_ARFCN_DCS 512 // 1st arfcn is 512
698 #define NBMAX_CARRIER_DCS 374 // 374 carriers for DCS1800.
699 #define MAX_TXPWR_DCS 15 // lowest power ctrl level value in DCS band
700 #define TXPWR_TURNING_POINT_DCS 28
701 // GSM850
702 #define FIRST_ARFCN_GSM850 128 // 1st arfcn is 128
703 #define NBMAX_CARRIER_GSM850 124 // 124 carriers for GSM850
704 #define NBMEAS_GSM850 3 // 3 measurement per frame TBD
705 #define MAX_TXPWR_GSM850 19 // lowest power ctrl level value in GSM band
706 // DUAL
707 #define FIRST_DCS_INDEX_DUAL 125 // 1st DCS index within the 498 continu list
708 #define NBMAX_CARRIER_DUAL 124+374 // 374 carriers for DCS1800 + 124 carriers for GSM900 Band
709 #define TXPWR_TURNING_POINT_DUAL 28
710 // DUALEXT
711 #define FIRST_DCS_INDEX_DUALEXT 175 // 1st DCS index within the 548 continu list
712 #define NBMAX_CARRIER_DUALEXT 174+374 // 374 carriers for DCS1800 + 174 carriers for E-GSM900 Band
713 #define TXPWR_TURNING_POINT_DUALEXT 28
714 // DUAL_US
715 #define FIRST_ARFCN_GSM850_DUAL_US 1 // 1st GSM850 index within the 423 continu list
716 #define FIRST_PCS_INDEX_DUAL_US 125 // 1st PCS index within the 423 continu list
717 #define NBMAX_CARRIER_DUAL_US 124+299 // 299 carriers for PCS1900 + 124 carriers for GSM850\ Band
718 #define NBMEAS_DUAL_US 4 // 4 measurements per frames.
719 #define TXPWR_TURNING_POINT_DUAL_US 28 // TBD
720
721
722 #define NBMAX_CARRIER NBMAX_CARRIER_DUALEXT //used in arrays for power measurement
723 //non optimized!!! (dynamic memory allocation to optimize)
724 #define BAND1 1
725 #define BAND2 2
726
727 #define NO_TXPWR 255 // sentinal value used with UWORD8 type.
728
729
730 //--------------------------------------------------------
731 // Receive level values.
732 //--------------------------------------------------------
733 #define RXLEV63 63 // max value for RXLEV.
734 #define IL_MIN 240 // minimum input level is -120 dbm.
735
736 //--------------------------------------------------------
737 // Max number of cell to report in MPHC_RXLEV_IND.
738 // Nb cells to check to see if cell of MPHC_NETWORK_SYNC_REQ has been detected
739 //--------------------------------------------------------
740 #define MAX_MEAS_RXLEV_IND_TRACE 10
741 #define NB_FQ_TO_CHK 4
742
743 /*--------------------------------------------------------*/
744 /* Max value for GSM Paging Parameters. */
745 /*--------------------------------------------------------*/
746 #define MAX_AG_BLKS_RES_NCOMB 7
747 #define MAX_AG_BLKS_RES_COMB 2
748 #define MAX_PG_BLOC_INDEX_NCOMB 8
749 #define MAX_PG_BLOC_INDEX_COMB 2
750 #define MAX_BS_PA_MFRMS 9
751
752 /*--------------------------------------------------------*/
753 /* Position of different blocs in a MF51. */
754 /*--------------------------------------------------------*/
755 #define NBCCH_POSITION 2 // Normal BCCH position in a MF51.
756 #define EBCCH_POSITION 6 // Extended BCCH position in a MF51.
757 #define CCCH_0 6
758 #define CCCH_1 12
759 #define CCCH_2 16
760 #define CCCH_3 22
761 #define CCCH_4 26
762 #define CCCH_5 32
763 #define CCCH_6 36
764 #define CCCH_7 42
765 #define CCCH_8 46
766 #define FB_0 0
767 #define FB_1 10
768 #define FB_2 20
769 #define FB_3 30
770 #define FB_4 40
771 #define SB_0 1
772 #define SB_1 11
773 #define SB_2 21
774 #define SB_3 31
775 #define SB_4 41
776
777 /*--------------------------------------------------------*/
778 /* System information position in the "si_bit_map". */
779 /*--------------------------------------------------------*/
780 #define SI_1 0x0001
781 #define SI_2 0x0002
782 #define SI_2BIS 0x0100
783 #define SI_2TER 0x0200
784 #define SI_3 0x0004
785 #define SI_4 0x0008
786 #define SI_7 0x0040
787 #define SI_8 0x0080
788 #define ALL_SI SI_1 | SI_2 | SI_2BIS | SI_2TER | SI_3 | SI_4 | SI_7 | SI_8
789
790 /*--------------------------------------------------------*/
791 /* CBCH position in the "smscb_bit_map". */
792 /*--------------------------------------------------------*/
793 #define CBCH_TB1 0x0001
794 #define CBCH_TB2 0x0002
795 #define CBCH_TB3 0x0004
796 #define CBCH_TB5 0x0008
797 #define CBCH_TB6 0x0010
798 #define CBCH_TB7 0x0020
799
800 #define CBCH_CONTINUOUS_READING 0
801 #define CBCH_SCHEDULED 1
802 #define CBCH_INACTIVE 2
803
804 /*--------------------------------------------------------*/
805 /* Channel type definitions for DEDICATED mode. */
806 /*--------------------------------------------------------*/
807
808 //TABLE/ CHAN TYPE
809 #define INVALID_CHANNEL 0
810 #define TCH_F 1
811 #define TCH_H 2
812 #define SDCCH_4 3
813 #define SDCCH_8 4
814 //END_TABLE/
815
816 /*--------------------------------------------------------*/
817 /* Channel mode definitions for DEDICATED. */
818 /*--------------------------------------------------------*/
819 #define SIG_ONLY_MODE 0 // signalling only
820 #define TCH_FS_MODE 1 // speech full rate
821 #define TCH_HS_MODE 2 // speech half rate
822 #define TCH_96_MODE 3 // data 9,6 kb/s
823 #define TCH_48F_MODE 4 // data 4,8 kb/s full rate
824 #define TCH_48H_MODE 5 // data 4,8 kb/s half rate
825 #define TCH_24F_MODE 6 // data 2,4 kb/s full rate
826 #define TCH_24H_MODE 7 // data 2,4 kb/s half rate
827 #define TCH_EFR_MODE 8 // enhanced full rate
828 #define TCH_144_MODE 9 // data 14,4 kb/s half rate
829 #if (AMR == 1)
830 #define TCH_AHS_MODE 10 // adaptative speech half rate
831 #define TCH_AFS_MODE 11 // adaptative speech full rate
832 #endif
833
834
835 /*--------------------------------------------------------*/
836 /* Layer 1 functional modes for "mode" setting pupose. */
837 /*--------------------------------------------------------*/
838 #define CS_MODE0 0 // functional mode at reset.
839 #define CS_MODE 1 // functional mode in CELL SELECTION.
840 #define I_MODE 2 // functional mode in IDLE.
841 #define CON_EST_MODE1 3 // functional mode in ACCESS (before 1st RA, for TOA convergency).
842 #define CON_EST_MODE2 4 // functional mode in ACCESS (after 1st RA).
843 #define DEDIC_MODE 5 // functional mode in DEDICATED.
844 #define DEDIC_MODE_HALF_DATA 6 // used only for TOA histogram length purpose.
845 #if L1_GPRS
846 #define PACKET_TRANSFER_MODE 7
847 #endif
848
849 /*--------------------------------------------------------*/
850 /* Error causes for MPHC_NO_BCCH message. */
851 /*--------------------------------------------------------*/
852 #define NO_FB_SB 0 // FB or SB not found.
853 #define NCC_NOT_PERMITTED 1 // Synchro OK! but PLMN not permitted.
854
855 /*--------------------------------------------------------*/
856 /* MFTAB constants and flags. */
857 /*--------------------------------------------------------*/
858 #define L1_MAX_FCT 5 /* Max number of fctions in a frame */
859 #define MFTAB_SIZE 20
860
861 /********************************/
862 /* Software register/flags */
863 /* definitions. */
864 /********************************/
865 #define NO_CTRL (TRUE_L << 0)
866 #define CTRL_MS (TRUE_L << 1)
867 #define CTRL_TX (TRUE_L << 2)
868 #define CTRL_RX (TRUE_L << 3)
869 #define CTRL_ADC (TRUE_L << 4)
870 #define CTRL_SYNC (TRUE_L << 5)
871 #define CTRL_ABORT (TRUE_L << 6)
872 #define CTRL_TEST (TRUE_L << 7)
873 #define CTRL_SYCB (TRUE_L << 8)
874 #define CTRL_FB_ABORT (TRUE_L << 9)
875 #if L1_GPRS
876 #define CTRL_PRACH (TRUE_L << 10)
877 #define CTRL_SYSINGLE (TRUE_L << 11)
878 #endif
879
880
881 /********************************/
882 /* MISC management */
883 /********************************/
884 #define GSM_CTL 0 // DSP ctrl for a GSM task
885 #define MISC_CTL 1 // DSP ctrl for a MISC task
886 #define GSM_MISC_CTL 2 // DSP ctrl for a GSM and MISC tasks
887
888 /********************************/
889 /* TOA management */
890 /********************************/
891 #define ISH_INVALID 128 // value used to disable the toa offset
892
893 /********************************/
894 /* AGC management */
895 /********************************/
896 #define DPAGC_FIFO_LEN 4
897 #define DPAGC_MAX_FLAG 1
898 #if (AMR == 1)
899 #define DPAGC_AMR_FIFO_LEN 4
900 #endif
901
902 /********************************/
903 /* ADC management */
904 /********************************/
905 #define ADC_DISABLED 0x0000
906 // Traffic part
907 #define ADC_MASK_RESET_TRAFFIC 0xFF00
908 #define ADC_NEXT_TRAFFIC_UL 0x0001
909 #define ADC_EACH_TRAFFIC_UL 0x0002
910 #define ADC_NEXT_TRAFFIC_DL 0x0004
911 #define ADC_EACH_TRAFFIC_DL 0x0008
912 #define ADC_EACH_RACH 0x0010
913
914
915 // Idle part
916 #define ADC_MASK_RESET_IDLE 0x00FF
917 #define ADC_NEXT_NORM_PAGING 0x0100
918 #define ADC_EACH_NORM_PAGING 0x0200
919 #define ADC_NEXT_MEAS_SESSION 0x0400
920 #define ADC_EACH_MEAS_SESSION 0x0800
921 #define ADC_NEXT_NORM_PAGING_REORG 0x1000
922 #define ADC_EACH_NORM_PAGING_REORG 0x2000
923
924
925 // CS_MODE0 part
926 #define ADC_NEXT_CS_MODE0 0x4000
927 #define ADC_EACH_CS_MODE0 0x8000
928
929
930 /********************************/
931 /* Neighbor BCCH priorities */
932 /********************************/
933
934 #define TOP_PRIORITY 0
935 #define HIGH_PRIORITY 1
936 #define NORMAL_PRIORITY 2
937
938 /********************************/
939 /* Driver constants definitions */
940 /********************************/
941
942 // Used to identify the 1st and last burst for offset management in Drivers.
943 #define BURST_1 0
944 #define BURST_2 1
945 #define BURST_3 2
946 #define BURST_4 3
947
948
949 // Identifier for all DSP tasks.
950 // ...RX & TX tasks identifiers.
951 #define NO_DSP_TASK 0 // No task.
952 #define NP_DSP_TASK 21 // Normal Paging reading task.
953 #define EP_DSP_TASK 22 // Extended Paging reading task.
954 #define NBS_DSP_TASK 19 // Normal BCCH serving reading task.
955 #define EBS_DSP_TASK 20 // Extended BCCH serving reading task.
956 #define NBN_DSP_TASK 17 // Normal BCCH neighbour reading task.
957 #define EBN_DSP_TASK 18 // Extended BCCH neighbour reading task.
958 #define ALLC_DSP_TASK 24 // CCCH reading task while performing FULL BCCH/CCCH reading task.
959 #define CB_DSP_TASK 25 // CBCH reading task.
960 #define DDL_DSP_TASK 26 // SDCCH/D (data) reading task.
961 #define ADL_DSP_TASK 27 // SDCCH/A (SACCH) reading task.
962 #define DUL_DSP_TASK 12 // SDCCH/D (data) transmit task.
963 #define AUL_DSP_TASK 11 // SDCCH/A (SACCH) transmit task.
964 #define RACH_DSP_TASK 10 // RACH transmit task.
965 #define TCHT_DSP_TASK 13 // TCH Traffic data DSP task id (RX or TX)
966 #define TCHA_DSP_TASK 14 // TCH SACCH data DSP task id (RX or TX)
967 #define TCHD_DSP_TASK 28 // TCH Traffic data DSP task id (RX or TX)
968
969 #define TCH_DTX_UL 15 // Replace UL task in DSP->MCU com. to say "burst not transmitted".
970
971 #if (L1_GPRS)
972 // Identifier for DSP tasks Packet dedicated.
973 // ...RX & TX tasks identifiers.
974 //------------------------------------------------------------------------
975 // WARNING ... Need to aligned following macro with MCU/DSP GPRS Interface
976 //------------------------------------------------------------------------
977 #define PNP_DSP_TASK 30
978 #define PEP_DSP_TASK 31
979 #define PALLC_DSP_TASK 32
980 #define PBS_DSP_TASK 33
981
982 #define PTCCH_DSP_TASK 33
983
984 #endif
985
986 // Identifier for measurement, FB / SB search tasks.
987 // Values 1,2,3 reserved for "number of measurements".
988 #define FB_DSP_TASK 5 // Freq. Burst reading task in Idle mode.
989 #define SB_DSP_TASK 6 // Sync. Burst reading task in Idle mode.
990 #define TCH_FB_DSP_TASK 8 // Freq. Burst reading task in Dedicated mode.
991 #define TCH_SB_DSP_TASK 9 // Sync. Burst reading task in Dedicated mode.
992 #define IDLE1 1
993
994 // Debug tasks
995 #define CHECKSUM_DSP_TASK 33
996 #define TST_NDB 35 // Checksum DSP->MCU
997 #define TST_DB 36 // DB communication check
998 #define INIT_VEGA 37
999 #define DSP_LOOP_C 38
1000
1001 // Identifier for measurement, FB / SB search tasks.
1002 // Values 1,2,3 reserved for "number of measurements".
1003 #define TCH_LOOP_A 31
1004 #define TCH_LOOP_B 32
1005
1006 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1007 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800)))
1008 #else
1009 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x09A0 - 0x800)))
1010 #endif
1011
1012 // bits in d_gsm_bgd_mgt - background task management
1013 #define B_DSPBGD_RECO 1 // start of reco in dsp background
1014 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background
1015 #define B_DSPBGD_STOP_RECO 256 // stop of reco in dsp background
1016 #define B_DSPBGD_STOP_UPD 512 // stop of alignement update in dsp background
1017
1018 // bit in d_pll_config
1019 #define B_32KHZ_CALIB (TRUE_L << 14) // force DSP in Idle1 during 32 khz calibration
1020 // ****************************************************************
1021 // NDB AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
1022 // ****************************************************************
1023 // bits in d_tch_mode
1024 #define B_EOTD (TRUE_L << 0) // EOTD mode
1025 #define B_PLAY_UL (TRUE_L << 3) // Play UL
1026 #define B_DCO_ON (TRUE_L << 4) // DCO ON/OFF
1027 #define B_AUDIO_ASYNC (TRUE_L << 1) // WCP reserved
1028
1029 // ****************************************************************
1030 // PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
1031 // ****************************************************************
1032 #define C_POND_RED 1L
1033 // below values are defined in the file l1_time.h
1034 //#define D_NSUBB_IDLE 296L
1035 //#define D_NSUBB_DEDIC 30L
1036 #define D_FB_THR_DET_IACQ 0x3333L
1037 #define D_FB_THR_DET_TRACK 0x28f6L
1038 #define D_DC_OFF_THRES 0x7fffL
1039 #define D_DUMMY_THRES 17408L
1040 #define D_DEM_POND_GEWL 26624L
1041 #define D_DEM_POND_RED 20152L
1042 #define D_HOLE 0L
1043 #define D_TRANSFER_RATE 0x6666L
1044
1045 // Full Rate vocoder definitions.
1046 #define D_MACCTHRESH1 7872L
1047 #define D_MLDT -4L
1048 #define D_MACCTHRESH 7872L
1049 #define D_GU 5772L
1050 #define D_GO 7872L
1051 #define D_ATTMAX 53L
1052 #define D_SM -892L
1053 #define D_B 208L
1054 #define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
1055 #define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
1056 #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
1057 #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
1058
1059 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1060 // Frequency burst definitions
1061 #define D_FB_MARGIN_BEG 24
1062 #define D_FB_MARGIN_END 22
1063
1064 // V42bis definitions
1065 #define D_V42B_SWITCH_HYST 16L
1066 #define D_V42B_SWITCH_MIN 64L
1067 #define D_V42B_SWITCH_MAX 250L
1068 #define D_V42B_RESET_DELAY 10L
1069
1070 // Latencies definitions
1071 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1072 // C.f. BUG1404
1073 #define D_LAT_MCU_BRIDGE 0x000FL
1074 #else
1075 #define D_LAT_MCU_BRIDGE 0x0009L
1076 #endif
1077
1078 #define D_LAT_MCU_HOM2SAM 0x000CL
1079
1080 #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
1081 #define D_LAT_DSP_AFTER_SAM 0x0004L
1082
1083 // Background Task in GSM mode: Initialization.
1084 #define D_GSM_BGD_MGT 0L
1085
1086 #if (CHIPSET == 4)
1087 #define D_MISC_CONFIG 0L
1088 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
1089 #define D_MISC_CONFIG 1L
1090 #else
1091 #define D_MISC_CONFIG 0L
1092 #endif
1093
1094 #endif
1095
1096 // Hall Rate vocoder and ched definitions.
1097
1098 #define D_SD_MIN_THR_TCHHS 37L
1099 #define D_MA_MIN_THR_TCHHS 344L
1100 #define D_MD_MAX_THR_TCHHS 2175L
1101 #define D_MD1_MAX_THR_TCHHS 138L
1102 #define D_SD_AV_THR_TCHHS 1845L
1103 #define D_WED_FIL_TC 0x7c00L
1104 #define D_WED_FIL_INI 4650L
1105 #define D_X_MIN 15L
1106 #define D_X_MAX 23L
1107 #define D_Y_MIN 703L
1108 #define D_Y_MAX 2460L
1109 #define D_SLOPE 135L
1110 #define D_WED_DIFF_THRESHOLD 406L
1111 #define D_MABFI_MIN_THR_TCHHS 5320L
1112 #define D_LDT_HR -5
1113 #define D_MACCTRESH_HR 6500
1114 #define D_MACCTRESH1_HR 6500
1115 #define D_GU_HR 2620
1116 #define D_GO_HR 3700
1117 #define D_B_HR 182
1118 #define D_SM_HR -1608
1119 #define D_ATTMAX_HR 53
1120
1121 // Enhanced Full Rate vocoder and ched definitions.
1122
1123 #define C_MLDT_EFR -4
1124 #define C_MACCTHRESH_EFR 8000
1125 #define C_MACCTHRESH1_EFR 8000
1126 #define C_GU_EFR 4522
1127 #define C_GO_EFR 6500
1128 #define C_B_EFR 174
1129 #define C_SM_EFR -878
1130 #define C_ATTMAX_EFR 53
1131 #define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
1132 #define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
1133 #define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
1134 #define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
1135
1136
1137 // Integrated Data Services definitions.
1138 #define D_MAX_OVSPD_UL 8
1139 // Detect frames containing 90% of 1s as synchro frames
1140 #define D_SYNC_THRES 0x3f50
1141 // IDLE frames are only frames with 100 % of 1s
1142 #define D_IDLE_THRES 0x4000
1143 #define D_M1_THRES 5
1144 #define D_MAX_OVSP_DL 8
1145
1146 // d_ra_act: bit field definition
1147 #define B_F48BLK 5
1148
1149 // Mask for b_itc information (d_ra_conf)
1150 #define CE_MASK 0x04
1151
1152 #define D_FACCH_THR 0
1153 #define D_DSP_TEST 0
1154 #define D_VERSION_NUMBER 0
1155 #define D_TI_VERSION 0
1156
1157
1158 /*------------------------------------------------------------------------------*/
1159 /* */
1160 /* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */
1161 /* ++++++++++++++++++++++++++++++++++++++++++ */
1162 /* */
1163 /*------------------------------------------------------------------------------*/
1164 // COMMUNICATION Interrupt definition
1165 //------------------------------------
1166 #define ALL_16BIT 0xffffL
1167 #define B_GSM_PAGE (TRUE_L << 0)
1168 #define B_GSM_TASK (TRUE_L << 1)
1169 #define B_MISC_PAGE (TRUE_L << 2)
1170 #define B_MISC_TASK (TRUE_L << 3)
1171
1172 #define B_GSM_PAGE_MASK (ALL_16BIT ^ B_GSM_PAGE)
1173 #define B_GSM_TASK_MASK (ALL_16BIT ^ B_GSM_TASK)
1174 #define B_MISC_PAGE_MASK (ALL_16BIT ^ B_MISC_PAGE)
1175 #define B_MISC_TASK_MASK (ALL_16BIT ^ B_MISC_TASK)
1176
1177 // Common definition
1178 //----------------------------------
1179 // Index to *_DEMOD* arrays.
1180 #define D_TOA 0 // Time Of Arrival.
1181 #define D_PM 1 // Power Measurement.
1182 #define D_ANGLE 2 // Angle (AFC correction)
1183 #define D_SNR 3 // Signal / Noise Ratio.
1184
1185 // Bit name/position definitions.
1186 #define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
1187 #define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused)
1188 #define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR).
1189 #define B_BLUD 15 // Uplink,Downlink data block Present. (1 for PRESENT).
1190 #define B_AF 14 // Activity bit: 1 if data block is valid.
1191 #define B_BFI 2 // Bad Frame Indicator
1192 #define B_UFI 0 // UNRELIABLE FRAME Indicator
1193 #define B_ECRC 9 // Enhanced full rate CRC bit
1194 #define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine
1195
1196 #if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
1197 #define FACCH_GOOD 10
1198 #define FACCH_BAD 11
1199 #endif
1200
1201 #if (AMR == 1)
1202 // Place of the RX type in the AMR block header
1203 #define RX_TYPE_SHIFT 3
1204 #define RX_TYPE_MASK 0x0038
1205
1206 // Place of the vocoder type in the AMR block header
1207 #define VOCODER_TYPE_SHIFT 0
1208 #define VOCODER_TYPE_MASK 0x0007
1209
1210 // List of the possible RX types in a_dd block
1211 #define SPEECH_GOOD 0
1212 #define SPEECH_DEGRADED 1
1213 #define ONSET 2
1214 #define SPEECH_BAD 3
1215 #define SID_FIRST 4
1216 #define SID_UPDATE 5
1217 #define SID_BAD 6
1218 #define AMR_NO_DATA 7
1219 #define AMR_INHIBIT 8
1220
1221 // List of possible RX types in RATSCCH block
1222 #define C_RATSCCH_GOOD 5
1223
1224 // List of the possible AMR channel rate
1225 #define AMR_CHANNEL_4_75 0
1226 #define AMR_CHANNEL_5_15 1
1227 #define AMR_CHANNEL_5_9 2
1228 #define AMR_CHANNEL_6_7 3
1229 #define AMR_CHANNEL_7_4 4
1230 #define AMR_CHANNEL_7_95 5
1231 #define AMR_CHANNEL_10_2 6
1232 #define AMR_CHANNEL_12_2 7
1233
1234 // Types of RATSCCH blocks
1235 #define C_RATSCCH_UNKNOWN 0
1236 #define C_RATSCCH_CMI_PHASE_REQ 1
1237 #define C_RATSCCH_AMR_CONFIG_REQ_MAIN 2
1238 #define C_RATSCCH_AMR_CONFIG_REQ_ALT 3
1239 #define C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE 4 // Alternative AMR_CONFIG_REQ with updates coming in the next THRES_REQ block
1240 #define C_RATSCCH_THRES_REQ 5
1241
1242 // These flags define a bitmap that indicates which AMR parameters are being modified by a RATSCCH
1243 #define C_AMR_CHANGE_CMIP 0
1244 #define C_AMR_CHANGE_ACS 1
1245 #define C_AMR_CHANGE_ICM 2
1246 #define C_AMR_CHANGE_THR1 3
1247 #define C_AMR_CHANGE_THR2 4
1248 #define C_AMR_CHANGE_THR3 5
1249 #define C_AMR_CHANGE_HYST1 6
1250 #define C_AMR_CHANGE_HYST2 7
1251 #define C_AMR_CHANGE_HYST3 8
1252
1253 // CMIP default value
1254 #define C_AMR_CMIP_DEFAULT 1 // According to ETSI specification 05.09, cmip is always 1 by default (new channel, handover...)
1255
1256 #endif
1257 // "d_ctrl_tch" bits positions for TCH configuration.
1258 #define B_CHAN_MODE 0
1259 #define B_CHAN_TYPE 4
1260 #define B_RESET_SACCH 6
1261 #define B_VOCODER_ON 7
1262 #define B_SYNC_TCH_UL 8
1263 #if (AMR == 1)
1264 #define B_SYNC_AMR 9
1265 #else
1266 #define B_SYNC_TCH_DL 9
1267 #endif
1268 #define B_STOP_TCH_UL 10
1269 #define B_STOP_TCH_DL 11
1270 #define B_TCH_LOOP 12
1271 #define B_SUBCHANNEL 15
1272
1273 // "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
1274 #define B_RAMP 0
1275 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1276 #define B_BULRAMPDEL 3 // Note: this name is changed
1277 #define B_BULRAMPDEL2 2 // Note: this name is changed
1278 #define B_BULRAMPDEL_BIS 9
1279 #define B_BULRAMPDEL2_BIS 10
1280 #endif
1281 #define B_AFC 4
1282
1283 // "d_ctrl_system" bits positions.
1284 #define B_TSQ 0
1285 #define B_BCCH_FREQ_IND 3
1286 #define B_TASK_ABORT 15 // Abort RF tasks for DSP.
1287
1288 /*
1289 * FreeCalypso Frankenstein: the following definition has been
1290 * imported from LoCosto version of l1_const.h; it is needed for
1291 * the LoCosto-based C code to compile.
1292 */
1293 #define C_BA_PM_MEAS (2)
1294
1295 // ****************************************************************
1296 // POLESTAR EVABOARD 3 REGISTERS & ADRESSES DEFINITIONS
1297 // ****************************************************************
1298
1299
1300 // DSP ADRESSES
1301 //--------------------
1302
1303 #define DB_SIZE (4*20L) // 4 pages of 20 words...
1304
1305 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1306 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1307 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1308 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
1309 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
1310 #define NDB_ADR 0xFFD001A8L // NDB start address : 268 words
1311 #define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words
1312
1313 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1314 #define DB2_R_PAGE_0 0xFFD00184L
1315 #define DB2_R_PAGE_1 0xFFD00188L
1316 #endif
1317 #else
1318 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1319 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1320 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
1321 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
1322 #define NDB_ADR 0xFFD000a0L // NDB start address : 268 words
1323 #define PARAM_ADR 0xFFD002b8L // PARAM start address : 57 words
1324 #endif
1325
1326 // ****************************************************************
1327 // ADC reading definitions
1328 // ****************************************************************
1329
1330 #define ADC_READ_PERIOD (40) //30 * 4.615 = 140ms
1331
1332
1333 // ****************************************************************
1334 // AGC: IL table identifier used by function Cust_get_agc_from_IL
1335 // ****************************************************************
1336 #define MAX_ID 1
1337 #define AV_ID 2
1338 #define PWR_ID 3
1339
1340 #if TESTMODE
1341 // ****************************************************************
1342 // Testmode: State of the continous mode
1343 // ****************************************************************
1344 #define TM_NO_CONTINUOUS 1 // continuous mode isn't active
1345 #define TM_START_RX_CONTINUOUS 2 // start the Rx continuous mode
1346 #define TM_START_TX_CONTINUOUS 3 // start the Tx continuous mode
1347 #define TM_CONTINUOUS 4 // Rx or Tx continuous mode
1348 #endif
1349 #if (AMR == 1)
1350 // ****************************************************************
1351 // AMR: Position of each AMR parameters in the AMR API buffer
1352 // ****************************************************************
1353 #define NSCB_INDEX 0
1354 #define NSCB_SHIFT 6
1355 #define ICMUL_INDEX 0
1356 #define ICMUL_SHIFT 4
1357 #define ICMDL_INDEX 0
1358 #define ICMDL_SHIFT 1
1359 #define ICMIUL_INDEX 0
1360 #define ICMIUL_SHIFT 3
1361 #define ICMIDL_INDEX 0
1362 #define ICMIDL_SHIFT 0
1363 #define ACSUL_INDEX 1
1364 #define ACSUL_SHIFT 0
1365 #define ACSDL_INDEX 1
1366 #define ACSDL_SHIFT 8
1367 #define THR1_INDEX 2
1368 #define THR1_SHIFT 0
1369 #define THR2_INDEX 2
1370 #define THR2_SHIFT 6
1371 #define THR3_INDEX 3
1372 #define THR3_SHIFT 8
1373 #define HYST1_INDEX 3
1374 #define HYST1_SHIFT 0
1375 #define HYST2_INDEX 3
1376 #define HYST2_SHIFT 4
1377 #define HYST3_INDEX 2
1378 #define HYST3_SHIFT 12
1379 #define NSYNC_INDEX 3
1380 #define NSYNC_SHIFT 14
1381 #define CMIP_INDEX 3
1382 #define CMIP_SHIFT 15
1383
1384 #define NSCB_MASK 0x0001
1385 #define ICM_MASK 0x0003
1386 #define ICMI_MASK 0x0001
1387 #define ACS_MASK 0x00FF
1388 #define THR_MASK 0x003F
1389 #define HYST_MASK 0x000F
1390 #define CMIP_MASK 0x0001
1391 #endif
1392