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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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-1:000000000000 0:b6a5e36de839
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1P_CMPL.C
4 *
5 * Filename l1p_cmpl.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1P_CMPL_C
11
12 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
13
14 #include "l1_macro.h"
15 #include "l1_confg.h"
16
17 #if L1_GPRS
18 #if (CODE_VERSION == SIMULATION)
19 #include <string.h>
20 #include "l1_types.h"
21 #include "sys_types.h"
22 #include "l1_const.h"
23 #include "l1_time.h"
24 #include "l1_signa.h"
25 #if TESTMODE
26 #include "l1tm_defty.h"
27 #endif
28 #if (AUDIO_TASK == 1)
29 #include "l1audio_const.h"
30 #include "l1audio_cust.h"
31 #include "l1audio_signa.h"
32 #include "l1audio_defty.h"
33 #include "l1audio_msgty.h"
34 #endif
35 #if (L1_GTT == 1)
36 #include "l1gtt_const.h"
37 #include "l1gtt_defty.h"
38 #endif
39 #if (L1_MP3 == 1)
40 #include "l1mp3_defty.h"
41 #endif
42 #if (L1_MIDI == 1)
43 #include "l1midi_defty.h"
44 #endif
45 #include "l1_defty.h"
46 #include "cust_os.h"
47 #include "l1_msgty.h"
48 #include "l1_varex.h"
49 #include "l1_proto.h"
50 #include "l1_tabs.h"
51 #include "l1_trace.h"
52 #if L2_L3_SIMUL
53 #include "l2_l3.h"
54 #include "hw_debug.h"
55 #endif
56
57 #include "l1p_cons.h"
58 #include "l1p_msgt.h"
59 #include "l1p_deft.h"
60 #include "l1p_vare.h"
61 #include "l1p_sign.h"
62
63 #if TESTMODE
64 #include "l1tm_msgty.h"
65 #include "l1tm_signa.h"
66 #endif
67
68 #include "macs_def.h"
69 #include "macs_cst.h"
70
71 #include "sim_cons.h"
72 #include "sim_def.h"
73 extern T_hw FAR hw;
74
75 #else
76 #include <string.h>
77 #include "l1_types.h"
78 #include "sys_types.h"
79 #include "l1_const.h"
80 #include "l1_time.h"
81 #include "l1_signa.h"
82 #if TESTMODE
83 #include "l1tm_defty.h"
84 #endif
85 #if (AUDIO_TASK == 1)
86 #include "l1audio_const.h"
87 #include "l1audio_cust.h"
88 #include "l1audio_signa.h"
89 #include "l1audio_defty.h"
90 #include "l1audio_msgty.h"
91 #endif
92 #if (L1_GTT == 1)
93 #include "l1gtt_const.h"
94 #include "l1gtt_defty.h"
95 #endif
96 #if (L1_MP3 == 1)
97 #include "l1mp3_defty.h"
98 #endif
99 #if (L1_MIDI == 1)
100 #include "l1midi_defty.h"
101 #endif
102 #include "l1_defty.h"
103 #include "cust_os.h"
104 #include "l1_msgty.h"
105 #include "l1_varex.h"
106 #include "l1_proto.h"
107 #include "l1_tabs.h"
108 #include "l1_trace.h"
109
110 #if L2_L3_SIMUL
111 #include "l2_l3.h"
112 #include "hw_debug.h"
113 #endif
114
115 #include "l1p_cons.h"
116 #include "l1p_msgt.h"
117 #include "l1p_deft.h"
118 #include "l1p_vare.h"
119 #include "l1p_sign.h"
120
121 #if TESTMODE
122 #include "l1tm_msgty.h"
123 #include "l1tm_signa.h"
124 #endif
125
126 #include "macs_def.h"
127 #include "macs_cst.h"
128 #endif
129
130 #if(RF_FAM == 61)
131 #include "l1_rf61.h"
132 #include "tpudrv61.h"
133 #endif
134
135 #include "l1_ctl.h"
136
137 /*-------------------------------------------------------*/
138 /* Prototypes of external functions used in this file. */
139 /*-------------------------------------------------------*/
140 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
141 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time);
142 void l1dmacro_rx_synth (UWORD16 arfcn);
143 void l1dmacro_agc (UWORD16 arfcn,WORD8 gain, UWORD8 lna
144 #if (RF_FAM == 61)
145 ,UWORD8 if_ctl
146 #endif
147 );
148 #if (L1_MADC_ON == 1)
149 #if (RF_FAM == 61)
150 void l1dmacro_rx_nb (UWORD16 arfcn, UWORD8 adc_active, UWORD8 csf_filter_choice
151 #if (NEW_SNR_THRESHOLD == 1)
152 ,UWORD8 saic_flag
153 #endif /* NEW_SNR_THRESHOLD */
154 );
155 #endif /* RF_FAM == 61*/
156 #else /* L1_MADC_ON == 1*/
157 void l1dmacro_rx_nb (UWORD16 arfcn);
158 #endif /* L1_MADC_ON == 1*/
159
160 void l1dmacro_afc (UWORD16 afc_value, UWORD8 win_id);
161 #if (RF_FAM == 61)
162 void l1dtpu_serv_rx_nb (UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
163 UWORD32 synchro_serv,UWORD32 new_offset,BOOL change_offset,
164 UWORD8 adc_active, UWORD8 csf_filter_choice,
165 UWORD8 if_ctl
166 #if (NEW_SNR_THRESHOLD == 1)
167 ,UWORD8 saic_flag
168 #endif /* NEW_SNR_THRESHOLD */
169 );
170
171 void l1pdtpu_serv_rx_nb (UWORD16 radio_freq, WORD8 agc, BOOL lna_off,
172 UWORD8 rx_id, UWORD32 offset_serv, UWORD8 num_rx,
173 UWORD8 rx_group_id, BOOL rx_done_flag,
174 UWORD8 adc_active, UWORD8 csf_filter_choice,
175 UWORD8 if_ctl
176 #if (NEW_SNR_THRESHOLD == 1)
177 ,UWORD8 saic_flag
178 #endif /* NEW_SNR_THRESHOLD */
179 );
180 #endif /* RF_FAM == 61*/
181 #if(RF_FAM != 61)
182 void l1dtpu_serv_rx_nb (UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
183 UWORD32 synchro_serv,UWORD32 new_offset,BOOL change_offset, UWORD8 adc_active);
184
185 void l1pdtpu_serv_rx_nb (UWORD16 radio_freq, WORD8 agc, BOOL lna_off,
186 UWORD8 rx_id, UWORD32 offset_serv, UWORD8 num_rx,
187 UWORD8 rx_group_id, BOOL rx_done_flag,UWORD8 adc_active);
188 #endif
189 void l1pdtpu_serv_tx (UWORD16 radio_freq, UWORD8 timing_advance,
190 UWORD32 offset_serv, UWORD8 tx_id, UWORD8 num_tx,
191 UWORD8 tx_group_id, UWORD8 switch_flag, BOOL burst_type,
192 BOOL rx_flag,UWORD8 adc_active);
193 UWORD8 l1pdtpu_interf_meas (UWORD16 radio_freq,
194 WORD8 agc,
195 UWORD8 lna_off,
196 UWORD8 meas_bitmap,
197 UWORD32 offset_serv,
198 UWORD16 win_id,
199 UWORD8 synchro_ts
200 #if(RF_FAM == 61)
201 ,UWORD8 if_ctl
202 #endif
203 );
204
205 void l1s_read_l3frm (UWORD8 pwr_level, API *info_address, UWORD32 task_rx);
206 void l1ps_macs_read (UWORD8 pr_table[8]);
207 void l1ps_macs_ctrl (void);
208 #if TESTMODE
209 void l1ps_tmode_macs_ctrl (void);
210 #endif
211 void l1pddsp_transfer_mslot_power (UWORD8 *txpwr, UWORD16 radio_freq, UWORD8 ul_bitmap);
212
213 void l1pddsp_single_tx_block (UWORD8 burst_nb, UWORD8 *data, UWORD8 tsc,
214 UWORD16 radio_freq);
215 void l1pddsp_idle_prach_data (BOOL polling, UWORD8 cs_type, UWORD16 channel_request_data,
216 UWORD8 bsic, UWORD16 radio_freq);
217 void l1pddsp_idle_prach_power (UWORD8 txpwr, UWORD16 radio_freq, UWORD8 ts);
218 #if FF_L1_IT_DSP_USF
219 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq,
220 UWORD8 timeslot_no, BOOL ptcch_dl, BOOL usf_interrupt);
221 #else
222 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq,
223 UWORD8 timeslot_no, BOOL ptcch_dl);
224 #endif
225
226 void l1pddsp_ul_ptcch_data (UWORD8 cs_type, UWORD16 channel_request_data, UWORD8 bsic, UWORD16 radio_freq, UWORD8 timeslot_no);
227 void l1ps_tcr_ctrl (UWORD8 pm_position);
228 void l1pd_afc (void);
229 void l1pddsp_interf_meas_ctrl (UWORD8 nb_meas_req);
230 void l1pddsp_meas_ctrl (UWORD8 nbmeas, UWORD8 pm_pos);
231 void maca_power_control (UWORD8 assignment_id, BOOL crc_error, WORD8 bcch_level, UWORD16 *radio_freq, WORD8 *burst_level, UWORD8 *pch);
232 WORD16 l1s_encode_rxlev (UWORD8 inlevel);
233
234 void l1pctl_pagc_ctrl (WORD8 *agc, UWORD8 *lna_off, UWORD16 radio_freq,UWORD8 serving_cell);
235 UWORD8 l1pctl_pagc_read (UWORD8 pm, UWORD16 radio_freq);
236 void l1pctl_transfer_agc_ctrl (WORD8 *agc, UWORD8 *lna_off, UWORD16 radio_freq);
237 void l1pctl_npc_agc_read (UWORD8 calibrated_IL[8],
238 T_DB_DSP_TO_MCU_GPRS *pdsp_db_r_ptr,
239 T_NDB_MCU_DSP_GPRS *pdsp_ndb_ptr);
240 void l1pctl_dpcma_agc_read (UWORD8 calibrated_IL[8],
241 T_DB_DSP_TO_MCU_GPRS *pdsp_db_r_ptr,
242 T_NDB_MCU_DSP_GPRS *pdsp_ndb_ptr,
243 UWORD8 pr_table[8]);
244 void l1pctl_dpcmb_agc_read (UWORD8 calibrated_IL[8],
245 T_DB_DSP_TO_MCU_GPRS *pdsp_db_r_ptr,
246 T_NDB_MCU_DSP_GPRS *pdsp_ndb_ptr,
247 UWORD8 pr_table[8]);
248 void l1ps_macs_header_decoding (UWORD8 rx_no, UWORD8 *tfi_result, UWORD8 *pr);
249 void l1ps_update_read_set_parameters(void);
250 void l1ps_bcch_meas_ctrl (UWORD8 ts);
251
252 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
253
254
255 /*-------------------------------------------------------*/
256 /* l1ps_ctrl_single() */
257 /*-------------------------------------------------------*/
258 /* */
259 /* Description: */
260 /* ------------ */
261 /* */
262 /* Input parameters: */
263 /* ----------------- */
264 /* */
265 /* Input parameters from globals: */
266 /* ------------------------------ */
267 /* */
268 /* Modified parameters from globals: */
269 /* --------------------------------- */
270 /* */
271 /*-------------------------------------------------------*/
272 void l1ps_ctrl_single(UWORD8 task, UWORD8 burst_id)
273 {
274 UWORD16 radio_freq;
275 T_INPUT_LEVEL *IL_info_ptr;
276 #if (RF_FAM == 61)
277 UWORD16 dco_algo_ctl_nb = 0;
278 UWORD8 if_ctl = 0;
279 UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS;
280 // By default we choose the hardware filter
281 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
282 #endif
283 #if (NEW_SNR_THRESHOLD == 1)
284 UWORD8 saic_flag=0;
285 #endif /* NEW_SNR_THRESHOLD */
286 // needs to be defined for maca_power_control() function call
287 #define DL_pwr_ctrl l1pa_l1ps_com.transfer.dl_pwr_ctrl
288
289 if((l1a_l1s_com.l1s_en_task[task] == TASK_ENABLED) &&
290 !(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
291 // Check the task semaphore. The control body is executed only
292 // when the task semaphore is 0. This semaphore can be set to
293 // 1 whenever L1A makes some changes to the task parameters.
294 {
295 // Catch ARFCN.
296 // *************
297
298 // Get ARFCN to be used for current control.
299 radio_freq = l1a_l1s_com.dedic_set.radio_freq;
300
301 // Traces and debug.
302 // ******************
303
304 #if (TRACE_TYPE==5) && FLOWCHART
305 trace_flowchart_dsp_tpu(dltsk_trace[task].name);
306 if(burst_id == BURST_1) trace_flowchart_dsptx(dltsk_trace[task].name);
307 #endif
308
309 #if (TRACE_TYPE!=0)
310 if (l1pa_l1ps_com.transfer.single_block.activity & (SINGLE_DL | SINGLE_UL)) // trace only if a window is programmed
311 trace_fct(CST_L1PS_CTRL_SINGLE, radio_freq);
312 #endif
313
314 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
315
316 /**************************************************************************/
317 /* Program DSP for mulstislot operation... */
318 /**************************************************************************/
319 /*===============*/
320 /* Downlink */
321 /*===============*/
322 if(l1pa_l1ps_com.transfer.single_block.activity & SINGLE_DL)
323 {
324 // Programs DSP.
325 #if FF_L1_IT_DSP_USF
326 l1pddsp_idle_rx_nb(burst_id,
327 l1pa_l1ps_com.transfer.aset->tsc,
328 radio_freq,
329 0,
330 FALSE,
331 FALSE);
332 #else
333 l1pddsp_idle_rx_nb(burst_id,
334 l1pa_l1ps_com.transfer.aset->tsc,
335 radio_freq,
336 0,
337 FALSE);
338 #endif
339
340 // Flag DSP programmation.
341 // Set "CTRL_RX" flag in the controle flag registers.
342 l1s.dsp_ctrl_reg |= CTRL_RX;
343 }
344
345 /*===============*/
346 /* Uplink */
347 /*===============*/
348 if(l1pa_l1ps_com.transfer.single_block.activity & SINGLE_UL)
349 {
350 // Pgme DSP for Single block TX on TS=3.
351 l1pddsp_single_tx_block (burst_id,
352 l1pa_l1ps_com.transfer.single_block.data_array,
353 l1pa_l1ps_com.transfer.aset->tsc,
354 radio_freq);
355
356 // TXPWR control needs to take into account ALPHA, GAMMA and C values, not only TXPWR MAX
357 // => maca_power_control() needs to be called
358 // Initialization of txpwr control values for all time slots
359 {
360 UWORD8 txpwr[8];
361 UWORD8 i;
362
363 // Call Uplink Transmit Power level algorithm
364 #if 0 /* LoCosto version */
365 maca_power_control(l1pa_l1ps_com.transfer.aset->assignment_id,
366 #else /* TCS211 reconstruction */
367 maca_power_control(DL_pwr_ctrl.assignment_id,
368 #endif
369 DL_pwr_ctrl.crc_error,
370 DL_pwr_ctrl.bcch_level,
371 DL_pwr_ctrl.radio_freq_tbl,
372 DL_pwr_ctrl.burst_level,
373 txpwr);
374
375 for(i = 0; i < 8; i++)
376 {
377 l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr[i] = txpwr[i];
378 }
379 }
380
381 // Pgme DSP for Transmit power on TS=3.
382 l1pddsp_transfer_mslot_power(l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr, radio_freq, 0x80 >> 3);
383
384 // Flag DSP programmation.
385 // Set "CTRL_TX" flag in the controle flag registers.
386 l1s.dsp_ctrl_reg |= CTRL_TX;
387 }
388
389 /**************************************************************************/
390 /* Program TPU for single slot operation... */
391 /**************************************************************************/
392
393 /*===============*/
394 /* Downlink */
395 /*===============*/
396 if(l1pa_l1ps_com.transfer.single_block.activity & SINGLE_DL)
397 {
398 WORD8 agc;
399 UWORD8 lna_off;
400
401 // Update AGC
402 l1pctl_transfer_agc_ctrl(&agc, &lna_off, radio_freq);
403
404
405 #if (RF_FAM == 61)
406 // Locosto DCO
407
408 cust_get_if_dco_ctl_algo(&dco_algo_ctl_nb, &if_ctl, (UWORD8) L1_IL_VALID,
409 l1a_l1s_com.Scell_used_IL.input_level ,
410 radio_freq, if_threshold);
411 l1ddsp_load_dco_ctl_algo_nb(dco_algo_ctl_nb);
412
413 #if (L1_SAIC != 0)
414 // If SAIC is enabled, call the low level SAIC control function
415 // NOTE: l1a_l1s_com.Scell_used_IL.input_level is updated within
416 // the l1pctl_transfer_agc_ctrl above
417 csf_filter_choice = l1ctl_saic(l1a_l1s_com.Scell_used_IL.input_level,l1a_l1s_com.mode
418 #if (NEW_SNR_THRESHOLD == 1)
419 ,task
420 ,&saic_flag
421 #endif
422 );
423 #endif
424
425 // tpu pgm...
426 l1pdtpu_serv_rx_nb(radio_freq,
427 agc,
428 lna_off,
429 0,
430 l1s.tpu_offset,
431 1,
432 1,
433 TRUE,
434 INACTIVE,
435 csf_filter_choice,
436 if_ctl
437 #if (NEW_SNR_THRESHOLD == 1)
438 ,saic_flag
439 #endif /* NEW_SNR_THRESHOLD */
440 );
441 #endif /* RF_FAM == 61*/
442 #if (RF_FAM != 61)
443 // tpu pgm...
444 #if (L1_SAIC != 0)
445 // If SAIC is enabled, call the low level SAIC control function
446 // NOTE: l1a_l1s_com.Scell_used_IL.input_level is updated within
447 // the l1pctl_transfer_agc_ctrl above
448 l1ctl_saic(l1a_l1s_com.Scell_used_IL.input_level,l1a_l1s_com.mode
449 #if (NEW_SNR_THRESHOLD == 1)
450 ,task
451 #endif
452 );
453 #endif
454
455
456 l1pdtpu_serv_rx_nb(radio_freq,
457 agc,
458 lna_off,
459 0,
460 l1s.tpu_offset,
461 1,
462 1,
463 TRUE,
464 INACTIVE);
465 #endif
466
467 // Set tpu window identifier for Synthesizer and
468 // according to last RX group position.
469 l1s.tpu_win = l1_config.params.rx_synth_load_split + RX_SPLIT_TABLE[0];
470
471 // Flag TPU programmation.
472 // Set "CTRL_RX" flag in the controle flag registers.
473 l1s.tpu_ctrl_reg |= CTRL_RX;
474 }
475
476 /*===============*/
477 /* Uplink */
478 /*===============*/
479 if(l1pa_l1ps_com.transfer.single_block.activity & SINGLE_UL)
480 {
481 // Program single block UL slot.
482 // ******************************
483 l1pdtpu_serv_tx(radio_freq,
484 l1pa_l1ps_com.transfer.aset->packet_ta.ta,
485 l1s.tpu_offset,
486 3,
487 1,
488 1,
489 0,
490 TX_NB_BURST,
491 l1pa_l1ps_com.transfer.single_block.activity & SINGLE_DL,
492 INACTIVE);
493
494 // Set tpu window identifier for Synthesizer and
495 // according to last TX group position.
496 l1s.tpu_win =(UWORD16)( (l1_config.params.rx_synth_load_split) +
497 ((UWORD16)3 * BP_SPLIT) + l1_config.params.tx_nb_load_split);
498
499 // Flag TPU programmation.
500 // Set "CTRL_TX" flag in the controle flag registers.
501 l1s.tpu_ctrl_reg |= CTRL_TX;
502
503 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
504 RTTL1_FILL_UL_NB(task, l1pa_l1ps_com.transfer.aset->packet_ta.ta, l1s.applied_txpwr)
505 #endif
506 }
507
508 /*===============*/
509 /* General */
510 /*===============*/
511 if(burst_id == BURST_4)
512 {
513 // Single block UL is now complete, reset its activity flag.
514 l1pa_l1ps_com.transfer.single_block.activity &= SINGLE_UL_MASK;
515
516 if(l1pa_l1ps_com.transfer.aset->allocated_tbf == SINGLE_BLOCK_DL)
517 {
518 // Single block UL is now complete.
519 l1pa_l1ps_com.transfer.single_block.activity &= SINGLE_DL_MASK;
520 }
521 }
522 } // End if(task enabled and semaphore false)
523
524 else
525 // When the task is aborted, we must continue to make dummy
526 // DSP programming to avoid communication mismatch due
527 // to C/W/R pipelining.
528 {
529 // Flag dummy DSP programmation.
530 // Set "CTRL_TX" flag in the controle flag registers.
531 l1s.dsp_ctrl_reg |= CTRL_TX;
532 }
533 }
534
535 /*-------------------------------------------------------*/
536 /* l1ps_ctrl_prach() */
537 /*-------------------------------------------------------*/
538 /* */
539 /* Description: */
540 /* ------------ */
541 /* */
542 /* Input parameters: */
543 /* ----------------- */
544 /* */
545 /* Input parameters from globals: */
546 /* ------------------------------ */
547 /* */
548 /* Modified parameters from globals: */
549 /* --------------------------------- */
550 /* */
551 /*-------------------------------------------------------*/
552 void l1ps_ctrl_prach(UWORD8 task, UWORD8 burst_id)
553 {
554 UWORD16 radio_freq;
555 UWORD8 txpwr;
556 UWORD8 adc_active = INACTIVE;
557
558 // Get ARFCN to be used for current control.
559 // ******************************************
560
561 radio_freq = l1pa_l1ps_com.p_idle_param.radio_freq;
562
563 // Get TXPWR value
564 txpwr = l1s.applied_txpwr;
565
566 // Traces and debug.
567 // ******************
568
569 #if (TRACE_TYPE!=0)
570 trace_fct(CST_L1S_CTRL_RACH, radio_freq);
571 #endif
572
573 #if (TRACE_TYPE==5) && FLOWCHART
574 trace_flowchart_dsp_tpu(dltsk_trace[task].name);
575 #endif
576
577 #if FF_L1_IT_DSP_USF
578 // Whenever the USF status is unknown then the PRACH control execution
579 // has to be postponed until DSP USF interrupt fires.
580 if (l1ps_macs_com.usf_status != USF_AWAITED)
581 {
582 #endif // FF_L1_IT_DSP_USF
583
584 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
585
586 #if FF_L1_IT_DSP_USF
587 // TPU and DSP have to be programmed for transmission only if the USF is
588 // good otherwise this is not a valid opportunity. If there was no USF
589 // uncertainty then the test is void.
590 if ( (l1ps_macs_com.usf_status != USF_IT_DSP)
591 || (((l1ps_dsp_com.pdsp_ndb_ptr->d_usf_updated_gprs >> ((7-0)*2)) & 0x0003) == USF_GOOD))
592 {
593 // Flags PRACH burst was controlled to TPU/DSP (not cancelled due to USF)
594 l1pa_l1ps_com.pra_info.prach_controlled = TRUE;
595 #endif // FF_L1_IT_DSP_USF
596
597 #if (CODE_VERSION!=SIMULATION)
598 #if (TRACE_TYPE==2 ) || (TRACE_TYPE==3)
599 L1_trace_string("PRA");
600 #endif
601 #endif
602
603 // Programs DSP for required task.
604 // ********************************
605 {
606 UWORD8 cs_type;
607
608 if (l1pa_l1ps_com.access_burst_type == ACC_BURST_8)
609 cs_type = CS_PAB8_TYPE;
610 else
611 cs_type = CS_PAB11_TYPE;
612
613 // ACCESS PRACH dsp control.
614 l1pddsp_idle_prach_data(FALSE,
615 cs_type,
616 l1pa_l1ps_com.pra_info.channel_request_data,
617 l1a_l1s_com.Scell_info.bsic,
618 radio_freq);
619 }
620
621 l1pddsp_idle_prach_power(txpwr,
622 radio_freq,
623 3);
624
625 // ADC measurement
626 // ***************
627
628 // check if during the RACH an ADC measurement must be performed
629 if (l1a_l1s_com.adc_mode & ADC_EACH_RACH) // perform ADC on each burst
630 adc_active = ACTIVE;
631
632 // Programs TPU for required task.
633 // ********************************
634
635 // tpu pgm...
636 l1dtpu_serv_tx_ra(radio_freq, l1s.tpu_offset, txpwr, adc_active);
637
638 // Set tpu window identifier for Power meas if any.
639 l1s.tpu_win = (3 * BP_SPLIT) + l1_config.params.tx_ra_load_split + l1_config.params.rx_synth_load_split;
640
641 // Store frame number to report to L3
642 l1pa_l1ps_com.pra_info.fn_to_report = l1s.next_time.fn;
643
644 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
645 RTTL1_FILL_UL_AB(task,txpwr)
646 #endif
647
648 // Flag DSP and TPU programmation.
649 // ********************************
650
651 // Set "CTRL_TX" flag in the controle flag register.
652 l1s.tpu_ctrl_reg |= CTRL_PRACH;
653 l1s.dsp_ctrl_reg |= CTRL_TX;
654
655 #if FF_L1_IT_DSP_USF
656 }// if ((l1ps_macs_com.usf_status != USF_IT_DSP) || USF_GOOD)
657 else
658 {
659 // PRACH has been cancelled because USF not FREE. Hence Read is skipped.
660 l1pa_l1ps_com.pra_info.prach_controlled = FALSE;
661 }
662 #endif
663
664 #if FF_L1_IT_DSP_USF
665 } // if (l1ps_macs_com.usf_status != USF_AWAITED)
666 #endif
667 }
668
669 /*-------------------------------------------------------*/
670 /* l1ps_ctrl_poll() */
671 /*-------------------------------------------------------*/
672 /* */
673 /* Description: */
674 /* ------------ */
675 /* */
676 /* Input parameters: */
677 /* ----------------- */
678 /* */
679 /* Input parameters from globals: */
680 /* ------------------------------ */
681 /* */
682 /* Modified parameters from globals: */
683 /* --------------------------------- */
684 /* */
685 /*-------------------------------------------------------*/
686 void l1ps_ctrl_poll(UWORD8 task, UWORD8 burst_id)
687 {
688 UWORD16 radio_freq;
689
690 // Get ARFCN to be used for current control.
691 // ******************************************
692 if(l1a_l1s_com.l1s_en_task[SINGLE] == TASK_ENABLED)
693 radio_freq = l1a_l1s_com.dedic_set.radio_freq;
694 else
695 radio_freq = l1pa_l1ps_com.p_idle_param.radio_freq;
696
697 // Traces and debug.
698 // ******************
699
700 #if (TRACE_TYPE!=0)
701 trace_fct(CST_L1PS_CTRL_POLL, radio_freq);
702 #endif
703
704 #if (TRACE_TYPE==5) && FLOWCHART
705 trace_flowchart_dsp_tpu(dltsk_trace[task].name);
706 #endif
707
708 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
709
710 #if (CODE_VERSION!=SIMULATION)
711 #if (TRACE_TYPE==2 ) || (TRACE_TYPE==3)
712 L1_trace_string("PRA");
713 #endif
714 #endif
715
716 // Programs DSP for required task.
717 // ********************************
718 {
719 UWORD8 cs_type;
720
721 cs_type = l1pa_l1ps_com.poll_info.pol_resp_type;
722
723 if ((cs_type == CS_PAB8_TYPE) || (cs_type == CS_PAB11_TYPE))
724 {
725 // IDLE POLLING PRACH dsp control.
726 l1pddsp_idle_prach_data(TRUE,
727 cs_type,
728 l1pa_l1ps_com.poll_info.chan_req.prach_data[0],
729 l1a_l1s_com.Scell_info.bsic,
730 radio_freq);
731
732 l1pddsp_idle_prach_power(l1s.applied_txpwr,
733 radio_freq,
734 3);
735
736 // Programs TPU for required task.
737 // ********************************
738 // tpu pgm...
739 l1dtpu_serv_tx_ra(radio_freq, l1s.tpu_offset, l1s.applied_txpwr,INACTIVE);
740
741 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
742 RTTL1_FILL_UL_AB(task,l1s.applied_txpwr)
743 #endif
744 }
745 else
746 {
747 UWORD8 tsc;
748
749 if(l1a_l1s_com.l1s_en_task[SINGLE] == TASK_ENABLED)
750 tsc = l1pa_l1ps_com.transfer.aset->tsc;
751 else
752 tsc = l1pa_l1ps_com.pccch.packet_chn_desc.tsc;
753
754 // Pgm DSP for Poll Response TX NB on TS=3.
755 l1pddsp_single_tx_block (burst_id,
756 l1pa_l1ps_com.poll_info.chan_req.cs1_data,
757 tsc,
758 radio_freq);
759
760 // Pgm DSP for Transmit power.
761 l1pddsp_transfer_mslot_power(l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr, radio_freq, 0x80>>3);
762
763 // Programs TPU for required task.
764 // ********************************
765 // tpu pgm...
766 l1dtpu_serv_tx_nb(radio_freq,
767 l1pa_l1ps_com.poll_info.timing_advance,
768 l1s.tpu_offset,
769 l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr[3],INACTIVE);
770
771 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
772 RTTL1_FILL_UL_NB(task, l1pa_l1ps_com.poll_info.timing_advance, l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr[3])
773 #endif
774 }
775 }
776
777
778 // Set tpu window identifier for Power meas if any.
779 l1s.tpu_win = (3 * BP_SPLIT) + l1_config.params.tx_nb_load_split + l1_config.params.rx_synth_load_split;
780
781 // Store frame number to report to L3
782 if (burst_id == BURST_4)
783 l1pa_l1ps_com.poll_info.fn_to_report = l1s.next_time.fn;
784
785 // Flag DSP and TPU programmation.
786 // ********************************
787
788 // Set "CTRL_TX" flag in the controle flag register.
789 l1s.tpu_ctrl_reg |= CTRL_TX;
790 l1s.dsp_ctrl_reg |= CTRL_TX;
791 }
792
793
794 #if (MOVE_IN_INTERNAL_RAM == 0) // Must be followed by the pragma used to duplicate the funtion in internal RAM
795 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
796
797 /*-------------------------------------------------------*/
798 /* l1s_ctrl_pdtch() */
799 /*-------------------------------------------------------*/
800 /* */
801 /* Description: This is the control function for Multislot Rx/Tx */
802 /* ------------ */
803 /* */
804 /* Input parameters: */
805 /* ----------------- */
806 /* */
807 /* Input parameters from globals: */
808 /* ------------------------------ */
809 /* */
810 /* Modified parameters from globals: */
811
812 /*-------------------------------------------------------*/
813 void l1ps_ctrl_pdtch(UWORD8 task, UWORD8 burst_id)
814 {
815 if((l1a_l1s_com.l1s_en_task[task] == TASK_ENABLED) &&
816 !(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
817 // Check the task semaphore. The control body is executed only
818 // when the task semaphore is 0. This semaphore can be set to
819 // 1 whenever L1A makes some changes to the task parameters.
820 {
821 UWORD16 radio_freq;
822 #if (RF_FAM == 61)
823 // By default we choose the hardware filter
824 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
825 #endif
826 #if (NEW_SNR_THRESHOLD == 1)
827 UWORD8 saic_flag=0;
828 #endif /* NEW_SNR_THRESHOLD */
829 // Traces and debug.
830 // ******************
831
832 #if (TRACE_TYPE==5) && FLOWCHART
833 trace_flowchart_dsp_tpu(dltsk_trace[PDTCH].name);
834 #endif
835
836 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
837
838 // Catch channel description and ARFCN.
839 // *************************************
840
841 // Get ARFCN to be used for current control. This ARFCN comes from
842 // the HOPPING algorithm called just before calling this function.
843 radio_freq = l1a_l1s_com.dedic_set.radio_freq;
844
845 #if (TRACE_TYPE==5) // in simulation trace only one time by frame
846 trace_fct(CST_L1PS_CTRL_PDTCH, radio_freq);
847 #endif
848
849 /**************************************************************************/
850 /* Program DSP for mulstislot operation... */
851 /**************************************************************************/
852 {
853 UWORD8 tx_allocation;
854
855 #if TESTMODE
856 if (l1_config.TestMode && (l1_config.tmode.tx_params.burst_data == 11))
857 // Call dummy MACS for CMU200 loopback mode
858 l1ps_tmode_macs_ctrl();
859 else
860 #endif
861 {
862 // Call MACS for Medium control, DATA control and RLC-MACS management
863 l1ps_macs_ctrl();
864 }
865
866 #if FF_L1_IT_DSP_USF
867 if (l1ps_macs_com.usf_status != USF_AWAITED)
868 {
869 #endif
870 // Compute tx_allocation mixing NB and RA allocations.
871 tx_allocation = l1ps_macs_com.tx_nb_allocation | l1ps_macs_com.tx_prach_allocation;
872
873 // Pgme TXPWR only if any UL.
874 if(tx_allocation)
875 {
876 // Pgme DSP for Transmit power.
877 // !!! Warning: This function must be called before l1pdtpu_serv_tx()
878 // !!! a_ctrl_abb_gprs is partly overwritten by l1pdtpu_serv_tx()
879 l1pddsp_transfer_mslot_power(l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr, radio_freq, tx_allocation);
880 }
881 #if FF_L1_IT_DSP_USF
882 }
883 #endif
884 }
885
886
887 /**************************************************************************/
888 /* Program TPU for mulstislot operation... */
889 /**************************************************************************/
890 {
891 WORD8 ts = 0;
892 UWORD8 rx_group_id = 0;
893 UWORD8 tx_group_id = 0;
894 BOOL pwr_programmed = FALSE;
895 UWORD8 bit_mask = 0x80;
896 WORD8 agc;
897 UWORD8 lna_off;
898 BOOL rx_done_flag;
899 BOOL adc_done = FALSE;
900 UWORD8 adc_active = INACTIVE;
901
902 #if (RF_FAM == 61)
903 UWORD16 dco_algo_ctl_nb = 0;
904 UWORD16 dco_algo_ctl_pw = 0;
905 UWORD8 if_ctl =0; //omaps00090550;
906 UWORD8 tot_num_rx = 0;
907 UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS;
908 #endif
909
910 // AGC and LNA_OFF processing
911 //---------------------------
912
913 #if FF_L1_IT_DSP_USF
914 #if L1_EDA
915 if (l1ps_macs_com.usf_status != USF_AWAITED)
916 #else
917 if (l1ps_macs_com.usf_status != USF_IT_DSP)
918 #endif
919 #endif
920 // Same AGC is used for all timeslots
921 l1pctl_transfer_agc_ctrl(&agc, &lna_off, radio_freq);
922
923 #if (L1_SAIC != 0)
924 // If SAIC is enabled, call the low level SAIC control function
925 // NOTE: l1a_l1s_com.Scell_used_IL.input_level is updated within
926 // the l1pctl_transfer_agc_ctrl above
927 csf_filter_choice = l1ctl_saic(l1a_l1s_com.Scell_used_IL.input_level,l1a_l1s_com.mode
928 #if (NEW_SNR_THRESHOLD == 1)
929 ,task
930 ,&saic_flag
931 #endif
932 );
933 #endif
934
935 while(ts < 8)
936 {
937
938 #if FF_L1_IT_DSP_USF
939 #if L1_EDA
940 //Depending on USF status got from DSP, RX allocation may change after
941 //receiving the USF interrupt due to USF status updates
942 if ((l1ps_macs_com.rx_allocation & bit_mask)
943 && (l1ps_macs_com.usf_status != USF_AWAITED))
944 #else
945 if ((l1ps_macs_com.rx_allocation & bit_mask)
946 && (l1ps_macs_com.usf_status != USF_IT_DSP))
947 #endif
948 #else
949 if(l1ps_macs_com.rx_allocation & bit_mask)
950 #endif
951 {
952 // We have detected the 1st RX slot number for a new RX group.
953
954 UWORD8 rx_id = ts; // Save 1st RX timeslot number.
955 UWORD8 num_rx = 1; // 1 RX in the RX group for the moment.
956
957 // Increment the RX group ID.
958 rx_group_id++;
959
960 #if (RF_FAM == 61)
961 //Increment the total number of RX slots
962 tot_num_rx++;
963 #endif
964
965 // Increment TS.
966 ts++;
967
968 // Jump on next timeslot to keep looking for contiguous RX slots.
969 bit_mask >>= 1;
970
971 // Look for more contiguous RX slots.
972 while((l1ps_macs_com.rx_allocation & bit_mask) && (ts < 8))
973 {
974 ts++;
975 num_rx++;
976 #if (RF_FAM == 61)
977 tot_num_rx++;
978 #endif
979 bit_mask >>= 1;
980 }
981
982 // Check if more RX bursts follow
983 if((l1ps_macs_com.rx_allocation << (ts+1)) & 0xFF)
984 rx_done_flag = FALSE;
985 else
986 rx_done_flag = TRUE;
987
988 #if (RF_FAM == 61) // Locosto DCO
989 if(rx_group_id == 1)
990 {
991 cust_get_if_dco_ctl_algo(&dco_algo_ctl_nb, &if_ctl, (UWORD8) L1_IL_VALID,
992 l1a_l1s_com.Scell_used_IL.input_level, radio_freq,if_threshold);
993 }
994
995 if(rx_done_flag == TRUE)
996 {
997 //dco_algo_ctl has 0000 00ZL
998 dco_algo_ctl_nb *= 0x55; // replicate 0000 00zL as ZLZL ZLZL
999 // ZLZLZLZL >> 2*(4-tot_num_rx) where i is the tot_num_rx would produce the
1000 // desired dco_algo_ctl_nb For Eg if tot_num_rx is 2 the desired pattern is
1001 // 0000 ZLZL
1002 dco_algo_ctl_nb = dco_algo_ctl_nb >> (2*( 4 - tot_num_rx));
1003 l1ddsp_load_dco_ctl_algo_nb(dco_algo_ctl_nb);
1004 }
1005 #endif
1006 // ADC measurement
1007 // ***************
1008 if (adc_done == FALSE)
1009 {
1010 // check if during the PDTCH burst an ADC measurement must be performed
1011 if (l1a_l1s_com.adc_mode & ADC_NEXT_TRAFFIC_DL) // perform ADC only one time
1012 {
1013 adc_active = ACTIVE;
1014 adc_done = TRUE;
1015 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_TRAFFIC; // reset in order to have only one ADC measurement in Traffic
1016 }
1017 else
1018 if (l1a_l1s_com.adc_mode & ADC_EACH_TRAFFIC_DL) // perform ADC on each period bloc
1019 if (l1s.actual_time.fn_mod104 == 10) //periodic with each PDTCH burst in frame 11 (frame with the lowest CPU load)
1020 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_traffic_period) // wait for the period
1021 {
1022 adc_active = ACTIVE;
1023 adc_done = TRUE;
1024 l1a_l1s_com.adc_cpt = 0;
1025 }
1026 }
1027
1028 // update the TPU with the new TOA if necessary
1029 if (rx_group_id == 1) // only if synchro performed
1030 l1ctl_update_TPU_with_toa();
1031
1032 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
1033 trace_fct(CST_L1PS_CTRL_PDTCH_DL_BURST0 + burst_id, radio_freq);
1034 #endif
1035
1036 // Program RX scenario.
1037 l1pdtpu_serv_rx_nb(radio_freq,
1038 agc,
1039 lna_off,
1040 rx_id,
1041 l1s.tpu_offset,
1042 num_rx,
1043 rx_group_id,
1044 rx_done_flag,adc_active
1045 #if (RF_FAM == 61)
1046 ,csf_filter_choice
1047 ,if_ctl
1048 #endif
1049 #if (NEW_SNR_THRESHOLD == 1)
1050 ,saic_flag
1051 #endif
1052 );
1053
1054 adc_active = INACTIVE; // ADC performed only on the first RX burst
1055
1056 // Set tpu window identifier for Synthesizer and
1057 // according to last RX group position.
1058 l1s.tpu_win = (l1_config.params.rx_synth_load_split) +
1059 ((UWORD16)rx_id * BP_SPLIT) + RX_SPLIT_TABLE[num_rx-1];
1060
1061
1062 // Set "CTRL_RX" flag in the controle flag registers.
1063 l1s.tpu_ctrl_reg |= CTRL_RX;
1064 l1s.dsp_ctrl_reg |= CTRL_RX;
1065 }
1066
1067 else
1068 #if FF_L1_IT_DSP_USF
1069 if ((l1ps_macs_com.tx_nb_allocation & bit_mask)
1070 && (l1ps_macs_com.usf_status != USF_AWAITED))
1071 #else
1072 if(l1ps_macs_com.tx_nb_allocation & bit_mask)
1073 #endif
1074 {
1075 // We have detected the 1st TX NB slot number for a new TX group.
1076
1077 UWORD8 tx_id = ts; // Save 1st TX timeslot number.
1078 UWORD8 num_tx = 1; // 1 RX in the TX group for the moment.
1079 UWORD8 switch_flag;
1080
1081 // Increment the TX group ID.
1082 tx_group_id++;
1083
1084 // Increment TS.
1085 ts++;
1086
1087 // Jump on next timeslot to keep looking for contiguous TX slots.
1088 bit_mask >>= 1;
1089
1090 // Look for more contiguous TX slots.
1091 while((l1ps_macs_com.tx_nb_allocation & bit_mask) && (ts < 8))
1092 {
1093 ts++;
1094 num_tx++;
1095 bit_mask >>= 1;
1096 }
1097
1098 // Detect special case: TX NB followed by PRACH.
1099 if(l1ps_macs_com.tx_prach_allocation & bit_mask)
1100 {
1101 switch_flag = 1;
1102 }
1103 else
1104 {
1105 switch_flag = 0;
1106 }
1107
1108 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
1109 trace_fct(CST_L1PS_CTRL_PDTCH_UL, radio_freq);
1110 #endif
1111
1112 // Program TN NB scenario.
1113 l1pdtpu_serv_tx(radio_freq,
1114 l1pa_l1ps_com.transfer.aset->packet_ta.ta,
1115 l1s.tpu_offset,
1116 tx_id,
1117 num_tx,
1118 tx_group_id,
1119 switch_flag,
1120 0, // Driver called for Normal Burst.
1121 TRUE,INACTIVE);// Flag RX in same frame as TX
1122
1123 // Set tpu window identifier for Synthesizer and
1124 // according to last TX group position.
1125 // TX offset = tx_id * BP_SPLIT
1126 // TX load = (num_tx-1) * BP_SPLIT + l1_config.params.tx_load_split
1127 l1s.tpu_win = (l1_config.params.rx_synth_load_split) +
1128 ((UWORD16)tx_id * BP_SPLIT) +
1129 ((UWORD16)(num_tx -1) * BP_SPLIT) +
1130 l1_config.params.tx_nb_load_split;
1131
1132 // Set "CTRL_TX" flag in the controle flag registers.
1133 l1s.tpu_ctrl_reg |= CTRL_TX;
1134 l1s.dsp_ctrl_reg |= CTRL_TX;
1135 }
1136
1137 else
1138 #if FF_L1_IT_DSP_USF
1139 if ((l1ps_macs_com.tx_prach_allocation & bit_mask)
1140 && (l1ps_macs_com.usf_status != USF_AWAITED))
1141 #else
1142 if(l1ps_macs_com.tx_prach_allocation & bit_mask)
1143 #endif
1144 {
1145 // We have detected a TX RA.
1146
1147 UWORD8 switch_flag;
1148
1149 // Increment the TX group ID.
1150 tx_group_id++;
1151
1152 // Jump on next timeslot.
1153 bit_mask >>= 1;
1154
1155 // Detect special case: PRACH followed by TX NB.
1156 if(l1ps_macs_com.tx_nb_allocation & bit_mask)
1157 {
1158 switch_flag = 1;
1159 }
1160 // Detect special case: PRACH followed by PRACH
1161 else if (l1ps_macs_com.tx_prach_allocation & bit_mask)
1162 {
1163 // Solution with DSP patch supporting PRACH|PRACH
1164 switch_flag = 2;
1165 }
1166 else
1167 {
1168 switch_flag = 0;
1169 }
1170
1171 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
1172 trace_fct(CST_L1PS_CTRL_PDTCH_RA, radio_freq);
1173 #endif
1174
1175 // Program TX RA scenario.
1176 l1pdtpu_serv_tx(radio_freq,
1177 l1pa_l1ps_com.transfer.aset->packet_ta.ta,
1178 l1s.tpu_offset,
1179 ts,
1180 1, // Driver is called for each PRACH.
1181 tx_group_id,
1182 switch_flag,
1183 TX_RA_BURST, // Driver called for PRACH Burst.
1184 TRUE,INACTIVE); // Flag RX in same frame as TX
1185
1186 // Set tpu window identifier for Synthesizer and
1187 // according to last TX group position.
1188 // TX offset = ts * BP_SPLIT
1189 // TX load = l1_config.params.tx_nb_load_split
1190 // original value of TX load (RACH) replaced by TX NB to take into account TX_NB|PRACH with max. TA
1191 l1s.tpu_win = (l1_config.params.rx_synth_load_split) +
1192 ((UWORD16)ts * BP_SPLIT) +
1193 l1_config.params.tx_nb_load_split;
1194
1195
1196 // Increment TS.
1197 ts++;
1198
1199 // Set "CTRL_TX" flag in the controle flag registers.
1200 l1s.tpu_ctrl_reg |= CTRL_TX;
1201 l1s.dsp_ctrl_reg |= CTRL_TX;
1202 }
1203
1204 else
1205 #if FF_L1_IT_DSP_USF
1206 if ((l1ps_macs_com.pwr_allocation & bit_mask)
1207 && (pwr_programmed == 0)
1208 && (l1ps_macs_com.usf_status != USF_AWAITED))
1209 #else
1210 if((l1ps_macs_com.pwr_allocation & bit_mask) && (pwr_programmed == 0))
1211 #endif
1212 {
1213 // We have detected a PWR allocation and no PWR programmed in current frame.
1214 if((l1pa_l1ps_com.transfer.aset->pc_meas_chan == FALSE) &&
1215 ((l1s.actual_time.t2 == 1) || (l1s.actual_time.t2 == 9)
1216 || (l1s.actual_time.t2 == 18)))
1217 {
1218 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
1219 trace_fct(CST_CTRL_PC_MEAS_CHAN, (UWORD32)(-1));
1220 #endif
1221
1222 // Measurement on the beacon (PC_MEAS_CHAN = 0)
1223 l1ps_bcch_meas_ctrl(ts);
1224 }
1225 else
1226 if(l1pa_l1ps_com.l1ps_en_meas & P_TCRMS_MEAS)
1227 {
1228 // Neighbour Measurement CTRL Phase
1229
1230 // Note: Test on l1s.forbid_meas can't be done from the fact that at this
1231 // level, l1s.forbid_meas is not set.
1232 // l1ps_ctrl_pdtch is called before CTRL of FB26/SB26/SBCNF26.
1233 if(!((l1s.actual_time.t2 == 23) &&
1234 ((l1s.task_status[FB26].current_status != INACTIVE) ||
1235 (l1s.task_status[SB26].current_status != INACTIVE) ||
1236 (l1s.task_status[SBCNF26].current_status != INACTIVE)))&&
1237 !(l1pa_l1ps_com.tcr_freq_list.new_list_present &&
1238 ((l1pa_l1ps_com.tcr_freq_list.cres_meas_report == 0) ||
1239 (l1pa_l1ps_com.tcr_freq_list.cres_meas_report == 103))))
1240 {
1241 if(!(l1pa_l1ps_com.meas_param & P_TCRMS_MEAS))
1242 {
1243 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
1244 trace_fct(CST_CTRL_TCR_MEAS_1, (UWORD32)(-1));
1245 #endif
1246
1247 l1ps_tcr_ctrl((UWORD8)ts);
1248 }
1249 }
1250 } // End of CTRL PDTCH phase
1251
1252 // Increment TS.
1253 ts++;
1254
1255 // Flag that a PWR as been programmed for current frame.
1256 pwr_programmed = TRUE;
1257
1258 // Jump on next timeslot.
1259 bit_mask >>= 1;
1260
1261 // Call PWR control function
1262
1263 }
1264
1265 else
1266 {
1267 // Increment TS.
1268 ts++;
1269
1270 // Jump on next timeslot.
1271 bit_mask >>= 1;
1272 }
1273
1274 } // End of "while(ts < 8)"
1275
1276 #if FF_L1_IT_DSP_USF
1277 if (l1ps_macs_com.usf_status != USF_AWAITED)
1278 #endif
1279 // Update of AFC
1280 l1pd_afc();
1281 }
1282 } // End if(task enabled and semaphore false)
1283
1284 else
1285 // When the task is aborted, we must continue to make dummy
1286 // DSP programming to avoid communication mismatch due
1287 // to C/W/R pipelining.
1288 {
1289 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
1290 trace_fct(CST_L1PS_CTRL_PDTCH_DUMMY, (UWORD32)(-1));
1291 #endif
1292
1293 // Flag dummy DSP programmation.
1294 // Set "CTRL_TX" flag in the controle flag registers.
1295 l1s.dsp_ctrl_reg |= CTRL_TX;
1296 }
1297
1298 }
1299 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
1300 #endif // MOVE_IN_INTERNAL_RAM
1301
1302
1303 /*-------------------------------------------------------*/
1304 /* l1s_read_single() */
1305 /*-------------------------------------------------------*/
1306 /* */
1307 /* Description: */
1308 /* ------------ */
1309 /* */
1310 /* Input parameters: */
1311 /* ----------------- */
1312 /* */
1313 /* Input parameters from globals: */
1314 /* ------------------------------ */
1315 /* */
1316 /* Modified parameters from globals: */
1317 /* --------------------------------- */
1318 /* */
1319 /*-------------------------------------------------------*/
1320 void l1ps_read_single(UWORD8 task, UWORD8 burst_id)
1321 {
1322 if((l1a_l1s_com.l1s_en_task[task] == TASK_ENABLED) &&
1323 !(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
1324 // Check the task semaphore. The control body is executed only
1325 // when the task semaphore is 0. This semaphore can be set to
1326 // 1 whenever L1A makes some changes to the task parameters.
1327 {
1328 // Read param updating...
1329 if (l1ps.read_param.new_set == TRUE)
1330 {
1331 // If it's the first Read phase of the block (first of the new TBF)
1332 if (burst_id == BURST_1)
1333 {
1334 // Update the "read_param" structure
1335 l1ps_update_read_set_parameters();
1336 }
1337 }
1338
1339 /*--------------------------------------------------------*/
1340 /* READ TRANSMIT TASK RESULTS... */
1341 /*--------------------------------------------------------*/
1342
1343 l1_check_com_mismatch(task);
1344
1345 // check PM error only in case of downlink single block
1346 if(l1ps.read_param.allocated_tbf == SINGLE_BLOCK_DL)
1347 {
1348 UWORD32 pm;
1349 pm = (l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[0] & 0xffff) >> 5;
1350 l1_check_pm_error(pm,task);
1351 }
1352
1353
1354 // Two phase access: downlink PDCH reading
1355 if((l1ps.read_param.allocated_tbf == TWO_PHASE_ACCESS)&&
1356 (l1ps_dsp_com.pdsp_db_r_ptr->d_task_d_gprs & (0x80 >> 0)))
1357 {
1358 UWORD8 IL_for_rxlev[8];
1359 UWORD8 pr_table[8];
1360
1361 if (burst_id == BURST_4)
1362 l1ps_macs_header_decoding(0, &(IL_for_rxlev[0]), &(pr_table[0]));
1363
1364 // Update AGC and extract IL for RXLEV
1365 //------------------------------------
1366 if (l1ps.read_param.dl_pwr_ctl.p0 == 255)
1367 {
1368 // No power control mode AGC algorithm
1369 l1pctl_npc_agc_read(IL_for_rxlev, l1ps_dsp_com.pdsp_db_r_ptr, l1ps_dsp_com.pdsp_ndb_ptr);
1370 }
1371 else
1372 {
1373 // Downlink power control AGC algorithms
1374 if (l1pa_l1ps_com.transfer.aset->dl_pwr_ctl.bts_pwr_ctl_mode == 0)
1375 {
1376 // BTS Power control mode A
1377 l1pctl_dpcma_agc_read(IL_for_rxlev, l1ps_dsp_com.pdsp_db_r_ptr, l1ps_dsp_com.pdsp_ndb_ptr, pr_table);
1378 }
1379 else
1380 {
1381 // BTS power control mode B
1382 l1pctl_dpcmb_agc_read(IL_for_rxlev, l1ps_dsp_com.pdsp_db_r_ptr, l1ps_dsp_com.pdsp_ndb_ptr, pr_table);
1383 }
1384 } // End of "AGC algorithm"
1385 }
1386
1387 #if (TRACE_TYPE!=0) && (TRACE_TYPE !=5)
1388 trace_fct(CST_L1PS_READ_SINGLE, l1a_l1s_com.Scell_info.radio_freq);
1389 #endif
1390
1391 // Read downlink DATA block from MCU/DSP interface.
1392 // *************************************************
1393 if(burst_id == BURST_4)
1394 {
1395 xSignalHeaderRec *msg;
1396
1397 #if (TRACE_TYPE==5) // in simulation trace only the 4th burst
1398 trace_fct(CST_L1PS_READ_SINGLE, l1a_l1s_com.Scell_info.radio_freq);
1399 #endif
1400
1401 if(l1ps.read_param.allocated_tbf == TWO_PHASE_ACCESS)
1402 // 2 phase ACCESS.
1403 {
1404 if((l1ps_dsp_com.pdsp_db_r_ptr->d_task_u_gprs & (0x80 >> 3)) &&
1405 (l1s.task_status[POLL].current_status == INACTIVE))
1406 // UL block sent...
1407 {
1408 // Send confirmation msg to L3/MACA.
1409 msg = os_alloc_sig(sizeof(T_MPHP_SINGLE_BLOCK_CON));
1410 DEBUGMSG(status,NU_ALLOC_ERR)
1411
1412 // Return "Single block" purpose.
1413 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->purpose =
1414 l1pa_l1ps_com.transfer.aset->assignment_command;
1415 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->assignment_id =
1416 l1pa_l1ps_com.transfer.aset->assignment_id;
1417
1418 // Return status and CRC error (CRC error not applicable).
1419 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->status = SINGLE_UL_DONE;
1420 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->dl_error_flag = 0;
1421
1422 // MSG is sent to L1A to stop PCCCH or CCCH/BCCH reading.
1423 msg->SignalCode = L1P_SINGLE_BLOCK_CON;
1424 os_send_sig(msg, L1C1_QUEUE);
1425 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
1426 }
1427
1428 if(l1ps_dsp_com.pdsp_db_r_ptr->d_task_d_gprs & (0x80 >> 0))
1429 // DL block received...
1430 {
1431 UWORD16 pwr_level;
1432
1433 #if (L1_FF_MULTIBAND == 1)
1434 UWORD16 operative_radio_freq;
1435 #endif /*(L1_FF_MULTIBAND == 1)*/
1436
1437 // this bloc doesn't compute the burst input level, so the last_input_level is used.
1438
1439 #if (L1_FF_MULTIBAND == 0)
1440
1441 pwr_level = l1a_l1s_com.last_input_level[l1a_l1s_com.Scell_info.radio_freq].input_level;
1442
1443 #else // L1_FF_MULTIBAND = 1 below
1444
1445 operative_radio_freq =
1446 l1_multiband_radio_freq_convert_into_operative_radio_freq(l1a_l1s_com.Scell_info.radio_freq);
1447 pwr_level = l1a_l1s_com.last_input_level[operative_radio_freq].input_level;
1448
1449 #endif // #if (L1_FF_MULTIBAND == 0) else
1450
1451
1452 // Read L3 frame block and send msg to L1A.
1453 l1s_read_l3frm(pwr_level, &(l1ps_dsp_com.pdsp_ndb_ptr->a_dd_gprs[0][0]), task);
1454 }
1455 }
1456 else
1457 {
1458 // SYNCHRO task is not schedule if we are in the specific case:
1459 // L1A is touching SYNCHRO parameters (tn_difference, dl_tn and dsp_scheduler_mode)
1460 // and leave L1A to go in HISR (L1S) in middle of the update (cf. BUG1339)
1461 if(l1a_l1s_com.task_param[SYNCHRO] == SEMAPHORE_RESET)
1462 {
1463 //----------------
1464 // Synchro back
1465 //----------------
1466 // Save the "timeslot difference" between new and old configuration
1467 // in "tn_difference".
1468 // tn_difference -> loaded with the number of timeslot to shift.
1469 // dl_tn -> loaded with the new timeslot.
1470 l1a_l1s_com.tn_difference += l1pa_l1ps_com.transfer.single_block.dl_tn_to_restore -
1471 l1a_l1s_com.dl_tn;
1472 l1a_l1s_com.dl_tn = l1pa_l1ps_com.transfer.single_block.dl_tn_to_restore;
1473
1474 // Select DSP Scheduler used in packet Idle (can be CCCH or PCCCH).
1475 if((l1a_l1s_com.l1s_en_task[ALLC] == TASK_ENABLED)
1476 || (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
1477 || (l1a_l1s_com.l1s_en_task[EP] == TASK_ENABLED))
1478 {
1479 // We are in CS Idle on CCCH.
1480 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER;
1481 }
1482
1483 // Enable SYNCHRO task.
1484 l1a_l1s_com.l1s_en_task[SYNCHRO] = TASK_ENABLED;
1485 }
1486
1487 //------------------
1488 // Confirmation msg
1489 //------------------
1490 // Common part...
1491 {
1492 // Send confirmation msg to L3/MACA.
1493 msg = os_alloc_sig(sizeof(T_MPHP_SINGLE_BLOCK_CON));
1494 DEBUGMSG(status,NU_ALLOC_ERR)
1495
1496
1497 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->purpose =
1498 l1pa_l1ps_com.transfer.aset->assignment_command;
1499 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->assignment_id =
1500 l1pa_l1ps_com.transfer.aset->assignment_id;
1501
1502 msg->SignalCode = L1P_SINGLE_BLOCK_CON;
1503
1504 // Disable SINGLE task.
1505 l1s.task_status[task].current_status = INACTIVE;
1506 l1a_l1s_com.l1s_en_task[task] = TASK_DISABLED;
1507 }
1508
1509 // Differentiated part...
1510
1511 if(l1pa_l1ps_com.transfer.aset->allocated_tbf == SINGLE_BLOCK_UL)
1512 // SINGLE UL task is complete.
1513 {
1514 // Return status and CRC error (CRC error not applicable).
1515 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->status = SINGLE_UL_DONE;
1516 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->dl_error_flag = 0;
1517 }
1518 else
1519 if(l1ps.read_param.allocated_tbf == SINGLE_BLOCK_DL)
1520 // SINGLE DL task is complete.
1521 {
1522 API *info_address;
1523 UWORD32 i,j;
1524 UWORD32 word32;
1525
1526 info_address = &(l1ps_dsp_com.pdsp_ndb_ptr->a_dd_gprs[0][0]);
1527
1528 // Return status and CRC error
1529 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->status = SINGLE_DL_DONE;
1530 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->dl_error_flag = ((*info_address & 0x0100) >> 8);
1531
1532 // Download data from API to message.
1533
1534 // Get 24 bytes info. from DSP: CS1 meaningful block is of size 12 UWORD16 data.
1535 // !!! WARNING: word32 type is for compatibility with chipset == 0.
1536 // Can be word16 if only chipset == 2 is used.
1537 for (j=0, i=0; i<12; i++)
1538 {
1539 word32 = info_address[4 + i]; // Get info word, rem: skip info. header.
1540 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->data_array[j++] = (word32 & 0x000000ff);
1541 ((T_MPHP_SINGLE_BLOCK_CON *)(msg->SigP))->data_array[j++] = (word32 & 0x0000ff00) >> 8;
1542 }
1543 }
1544
1545 // send message...
1546 os_send_sig(msg, L1C1_QUEUE);
1547 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
1548
1549 } // End else (!TWO_PHASE_ACCESS)
1550 }
1551
1552 // Set flag used to change the read page at the end of "l1_synch".
1553 l1s_dsp_com.dsp_r_page_used = TRUE;
1554
1555 } // End if(task enabled and semaphore false)
1556
1557 else
1558 // When the task is aborted, we must continue to make dummy
1559 // DSP/TPU programming to avoid communication mismatch due
1560 // to C/W/R pipelining. Dummy MCU/DSP reading is also done.
1561 {
1562 // Set flag used to change the read page at the end of "l1_synch".
1563 l1s_dsp_com.dsp_r_page_used = TRUE;
1564 }
1565 }
1566
1567 #if (MOVE_IN_INTERNAL_RAM == 0) // Must be followed by the pragma used to duplicate the funtion in internal RAM
1568 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
1569
1570 /*-------------------------------------------------------*/
1571 /* l1ps_read_pdtch() */
1572 /*-------------------------------------------------------*/
1573 /* */
1574 /* Description: */
1575 /* ------------ */
1576 /* */
1577 /* Input parameters: */
1578 /* ----------------- */
1579 /* */
1580 /* Input parameters from globals: */
1581 /* ------------------------------ */
1582 /* */
1583 /* Modified parameters from globals: */
1584 /* --------------------------------- */
1585 /* */
1586 /*-------------------------------------------------------*/
1587 void l1ps_read_pdtch(UWORD8 task, UWORD8 burst_id)
1588 {
1589 if((l1a_l1s_com.l1s_en_task[task] == TASK_ENABLED) &&
1590 !(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
1591 // Check the task semaphore. The control body is executed only
1592 // when the task semaphore is 0. This semaphore can be set to
1593 // 1 whenever L1A makes some changes to the task parameters.
1594 {
1595 BOOL beacon;
1596 T_INPUT_LEVEL *IL_info_ptr;
1597 UWORD16 radio_freq;
1598 WORD8 ts = 0;
1599 UWORD8 bit_mask = 0x80;
1600 WORD8 bcch_level;
1601 UWORD8 rx_no = 0;
1602 BOOL first_valid_block = TRUE;
1603 BOOL crc_error = TRUE;
1604 UWORD8 i;
1605 UWORD32 best_snr = 0;
1606 UWORD32 best_angle = 0;
1607 UWORD32 best_pm = 0;
1608 UWORD8 IL_for_rxlev[8], pr_table[8];
1609 WORD16 best_rxlev_accu = 0;
1610
1611
1612 static BOOL crc_error_tbl[8] = {TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE};
1613 static WORD16 rxlev_accu[8] = {0, 0, 0, 0, 0, 0, 0, 0};
1614 static WORD8 burst_level[4] = {(WORD8)0x80, (WORD8)0x80, (WORD8)0x80, (WORD8)0x80};
1615 static UWORD16 radio_freq_tbl[4];
1616 static UWORD32 toa_val[4] = {0, 0, 0, 0};
1617 static UWORD32 snr_val[4] = {0, 0, 0, 0};
1618
1619 #if TESTMODE
1620 xSignalHeaderRec *msg;
1621 static UWORD32 tm_pm_fullres = 0;
1622 static UWORD32 tm_snr = 0;
1623 static UWORD32 tm_toa = 0;
1624 static WORD16 tm_angle = 0;
1625 #endif
1626
1627
1628 #define burst_number l1ps_dsp_com.pdsp_db_r_ptr->d_burst_nb_gprs
1629 #define DL_pwr_ctrl l1pa_l1ps_com.transfer.dl_pwr_ctrl
1630
1631 // Read parameters updating
1632 // *************************
1633
1634 // ***********
1635 // * WARNING *
1636 // ***********
1637
1638 // Because of the STI implementation, the parameters under the "l1pa_l1ps_com.transfer.aset"
1639 // structure mustn't be used in the Read PDTCH functions
1640 // This is due to the following case that may happen:
1641 //
1642 // C|W R |
1643 // |C W R |
1644 // | C W R| TBF 1
1645 // | C W|R <--------------------------- (2) This "read phase" must use the TBF 1 parameters while "aset" has already been updated
1646 //---------------------- so the read_param structure is used
1647 // | C|W R <------------------------- (3) The read_param is updated with TBF 2 parameters
1648 // | |C W R at the beguining of the first Read of TBF 2
1649 // | | C W R TBF 2 so when (l1ps.read_param.new_set = TRUE and burst_id = BURST_1)
1650 // | | C W R
1651 // ^
1652 // (1) TBF 2 starting time detected on this frame (no SYNCHRO change needed between TBF1 and TBF 2)
1653 // --> aset parameters updated to TBF 2
1654 // --> l1ps.read_param.new_set set to TRUE
1655
1656 // If a new TBF has been enabled...
1657 if (l1ps.read_param.new_set == TRUE)
1658 {
1659 // If it's the first Read phase of the block (first of the new TBF)
1660 if (burst_id == BURST_1)
1661 {
1662 // Update the "read_param" structure
1663 l1ps_update_read_set_parameters();
1664 }
1665 }
1666
1667 // Traces and debug.
1668 // ******************
1669
1670 l1_check_com_mismatch(task);
1671
1672 radio_freq = l1a_l1s_com.dedic_set.radio_freq_dd;
1673
1674 if(l1ps.read_param.pc_meas_chan)
1675 {
1676 radio_freq_tbl[burst_number] = radio_freq;
1677 }
1678 else
1679 {
1680 radio_freq_tbl[burst_number] = l1a_l1s_com.Scell_info.radio_freq;
1681 }
1682
1683 if (radio_freq == l1a_l1s_com.Scell_info.radio_freq)
1684 {
1685 beacon=1;
1686 IL_info_ptr = &l1a_l1s_com.Scell_info.traffic_meas_beacon;
1687 }
1688 else
1689 {
1690 beacon=0;
1691 IL_info_ptr = &l1a_l1s_com.Scell_info.traffic_meas;
1692 }
1693
1694 // Call maca_power_control() in order to get TXPWR value
1695 if(l1ps_dsp_com.pdsp_db_r_ptr->d_burst_nb_gprs == 2)
1696 {
1697 UWORD8 txpwr[8];
1698 UWORD8 i;
1699
1700 // Due to the CWR pipeleine, maca_power_control() has to be called before the
1701 // CTRL of the first PDTCH i.e. in l1ps_ctrl_pdtch(). It means that crc_error,
1702 // radio_freq_tbl[], burst_level[] and bcch_level information are stored on
1703 // burst4 of READ phase ("l1ps_ctrl_pdtch()") to be used on burst4 of CTRL phase.
1704
1705 // Call Uplink Transmit Power level algorithm
1706 #if 0 /* LoCosto version */
1707 maca_power_control(l1ps.read_param.assignment_id,
1708 #else /* TCS211 reconstruction */
1709 maca_power_control(DL_pwr_ctrl.assignment_id,
1710 #endif
1711 DL_pwr_ctrl.crc_error,
1712 DL_pwr_ctrl.bcch_level,
1713 DL_pwr_ctrl.radio_freq_tbl,
1714 DL_pwr_ctrl.burst_level,
1715 txpwr);
1716
1717 #if TESTMODE
1718 if(!l1_config.TestMode)
1719 #endif
1720 {
1721 for(i = 0; i < 8; i++)
1722 {
1723 l1pa_l1ps_com.transfer.dl_pwr_ctrl.txpwr[i] = txpwr[i];
1724 }
1725 }
1726 }
1727
1728
1729 if(l1ps_dsp_com.pdsp_db_r_ptr->d_burst_nb_gprs == 3)
1730 /*---------------------------------------------------*/
1731 /* Complete PDTCH DL block has been processed by DSP */
1732 /*---------------------------------------------------*/
1733 {
1734 #if (TRACE_TYPE == 5) // in simulation trace only the latest burst
1735 trace_fct(CST_L1PS_READ_PDTCH, radio_freq);
1736 #endif
1737
1738 // Call MACS...
1739 l1ps_macs_read(pr_table);
1740 }
1741
1742 // Update AGC and extract IL for RXLEV
1743 //------------------------------------
1744 if (l1ps.read_param.dl_pwr_ctl.p0 == 255)
1745 {
1746 // No power control mode AGC algorithm
1747 l1pctl_npc_agc_read(IL_for_rxlev, l1ps_dsp_com.pdsp_db_r_ptr, l1ps_dsp_com.pdsp_ndb_ptr);
1748 }
1749 else
1750 {
1751 // Downlink power control AGC algorithms
1752 if (l1ps.read_param.dl_pwr_ctl.bts_pwr_ctl_mode == 0)
1753 {
1754 // BTS Power control mode A
1755 l1pctl_dpcma_agc_read(IL_for_rxlev, l1ps_dsp_com.pdsp_db_r_ptr, l1ps_dsp_com.pdsp_ndb_ptr, pr_table);
1756 }
1757 else
1758 {
1759 // BTS power control mode B
1760 l1pctl_dpcmb_agc_read(IL_for_rxlev, l1ps_dsp_com.pdsp_db_r_ptr, l1ps_dsp_com.pdsp_ndb_ptr, pr_table);
1761 }
1762 } // End of "AGC algorithm"
1763
1764 // TOA algorithm is called with toa/snr pair from last block (N-1)
1765 // Feed TOA histogram with values from good bursts (crc_error = FALSE)
1766 // otherwise input snr = 0.
1767 #if (TOA_ALGO != 0)
1768 // Good block, TOA from TS=0
1769 #if (TOA_ALGO == 2)
1770 if(l1s.toa_var.toa_snr_mask == 0)
1771 #else
1772 if(l1s.toa_snr_mask == 0)
1773 #endif
1774 {
1775 #if (TOA_ALGO == 2)
1776 {
1777 UWORD32 snr_temp;
1778 snr_temp = (crc_error_tbl[0] == FALSE) ? snr_val[burst_id] : 0;
1779 l1s.toa_var.toa_shift = l1ctl_toa(TOA_RUN, l1a_l1s_com.mode, snr_temp, toa_val[burst_id]);
1780 }
1781 #else
1782 {
1783 /* FreeCalypso TCS211 reconstruction */
1784 if (crc_error_tbl[0] == FALSE)
1785 {
1786 l1s.toa_shift = l1ctl_toa(TOA_RUN, l1a_l1s_com.mode,
1787 snr_val[burst_id], toa_val[burst_id],
1788 &l1s.toa_update, &l1s.toa_period_count
1789 #if (FF_L1_FAST_DECODING == 1)
1790 ,0
1791 #endif
1792 );
1793 }
1794 else
1795 {
1796 l1s.toa_shift = l1ctl_toa(TOA_RUN, l1a_l1s_com.mode,
1797 0, toa_val[burst_id],
1798 &l1s.toa_update, &l1s.toa_period_count
1799 #if (FF_L1_FAST_DECODING == 1)
1800 ,0
1801 #endif
1802 );
1803 }
1804 }
1805 #endif
1806 }
1807 #endif
1808
1809 /*---------------------------------------------------*/
1810 /* Read burst demodulation info for control algos */
1811 /* Use all burst results to feed the algos. */
1812 /*---------------------------------------------------*/
1813 while(ts < 8)
1814 {
1815 if(l1ps_dsp_com.pdsp_db_r_ptr->d_task_d_gprs & bit_mask)
1816 {
1817 UWORD32 toa;
1818 UWORD32 pm;
1819 UWORD32 angle;
1820 UWORD32 snr;
1821 WORD8 rxlev;
1822
1823 // Read control results and feed control algorithms.
1824 // **************************************************
1825
1826 // Read control information.
1827 toa = l1ps_dsp_com.pdsp_db_r_ptr->a_burst_toa_gprs[ts] & 0xffff;
1828 pm = (l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[ts] & 0xffff)>>5;
1829 angle = l1ps_dsp_com.pdsp_db_r_ptr->a_burst_angle_gprs[ts] & 0xffff;
1830 snr = l1ps_dsp_com.pdsp_db_r_ptr->a_burst_snr_gprs[ts] & 0xffff;
1831
1832 #if (TRACE_TYPE != 0) && (TRACE_TYPE != 5) // for debug trace all bursts
1833 trace_fct(CST_L1PS_READ_PDTCH_BURST, (UWORD32)(-1));
1834 #endif
1835
1836 l1_check_pm_error(pm,task);
1837
1838 #if TESTMODE
1839 // Test mode stats
1840 if (l1_config.TestMode)
1841 {
1842 if (bit_mask & l1_config.tmode.stats_config.stat_gprs_slots)
1843 {
1844 tm_pm_fullres += (l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[ts] & 0xffff);
1845 tm_snr += snr;
1846 tm_toa += toa;
1847 tm_angle += (WORD16) angle; // signed
1848 }
1849 }
1850 #endif
1851
1852 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1853 RTTL1_FILL_DL_BURST(angle, snr, l1s.afc, task, pm, toa, IL_for_rxlev[ts])
1854 #endif
1855 #if 0 //(TRACE_TYPE == 1) || (TRACE_TYPE == 4) // TCS211 reconstruction
1856 l1_trace_burst_param(angle, snr, l1s.afc, task, pm, toa, IL_for_rxlev[ts]);
1857 #endif
1858 #if (BURST_PARAM_LOG_ENABLE == 1)
1859 l1_log_burst_param(angle, snr, l1s.afc, task, pm, toa, IL_for_rxlev[ts]);
1860 #endif
1861
1862 //Look for the pairs angle, snr with the maximum snr
1863 if (snr > best_snr)
1864 {
1865 best_snr = snr;
1866 best_angle = angle;
1867 best_pm = pm;
1868 }
1869
1870 // store toa value from first TS
1871 if (ts==0)
1872 {
1873 toa_val[burst_id] = toa;
1874 snr_val[burst_id] = snr;
1875 }
1876
1877 // Store Received Signal Level to be used in Uplink Transmit Power Algorithm.
1878
1879 // Compute RXLEV
1880 rxlev = l1s_encode_rxlev(IL_for_rxlev[ts]);
1881
1882 // Find first correct PDTCH, save RXLEV and CRC
1883 if(!crc_error_tbl[ts] && first_valid_block)
1884 {
1885 if(l1ps.read_param.pc_meas_chan)
1886 {
1887 burst_level[burst_number] = rxlev;
1888 }
1889 else
1890 {
1891 burst_level[burst_number] = (WORD8)0x80;
1892 }
1893
1894 // Measures on first valid block have been performed. Reset flag.
1895 first_valid_block = FALSE;
1896
1897 // Save crc_error
1898 crc_error = crc_error_tbl[ts];
1899
1900 } // End of measurements storage
1901
1902 // If All PDTCH are incorrect (bad CRC) save RXLEV and CRC of the best PDTCH
1903 if(first_valid_block)
1904 {
1905 rxlev_accu[ts] += rxlev;
1906
1907 if(rxlev_accu[ts] > best_rxlev_accu)
1908 {
1909 best_rxlev_accu = rxlev_accu[ts];
1910 crc_error = crc_error_tbl[ts];
1911
1912 if(l1ps.read_param.pc_meas_chan)
1913 {
1914 burst_level[burst_number] = rxlev;
1915 }
1916 else
1917 {
1918 burst_level[burst_number] = (WORD8)0x80;
1919 }
1920 }
1921 }
1922
1923 // Determine first valid block to be used in next radio block
1924 if(l1ps_dsp_com.pdsp_db_r_ptr->d_burst_nb_gprs == 3)
1925 /*---------------------------------------------------*/
1926 /* Complete PDTCH DL block has been processed by DSP */
1927 /*---------------------------------------------------*/
1928 {
1929 crc_error_tbl[ts] = ((l1ps_dsp_com.pdsp_ndb_ptr->a_dd_gprs[rx_no][0] & 0x0100) >> 8);
1930
1931 // Increment Rx burst number
1932 rx_no++;
1933 }
1934
1935 #if TRACE_TYPE==3
1936 stats_samples_nb(toa,pm,angle,snr,burst_id,task);
1937 #endif
1938
1939 } // End of if(l1ps_dsp_com.pdsp_db_r_ptr->d_task_d_gprs & bit_mask)
1940
1941 // Increment timeslot
1942 ts++;
1943
1944 // Shift Mask.
1945 bit_mask >>= 1;
1946
1947 } // End of while(ts < 8)
1948
1949 // AFC control algorithm is called with values retrieved from
1950 // burst with max. snr
1951 // AFC algorithm is called on bursts 0 and 2: this is sufficient to
1952 // have a correct behavior and this permits to gain CPU
1953 // Update AFC: Call AFC control function (KALMAN filter).
1954 #if AFC_ALGO
1955 #if TESTMODE
1956 if (l1_config.afc_enable)
1957 #endif
1958 {
1959 if((burst_id == 0) || (burst_id == 2))
1960 #if (VCXO_ALGO == 0)
1961 l1s.afc = l1ctl_afc(AFC_CLOSED_LOOP, &l1s.afc_frame_count, (WORD16)best_angle, best_snr, radio_freq);
1962 #else
1963 l1s.afc = l1ctl_afc(AFC_CLOSED_LOOP, &l1s.afc_frame_count, (WORD16)best_angle, best_snr, radio_freq,l1a_l1s_com.mode);
1964 #endif
1965 }
1966 #endif
1967
1968 #if (TRACE_TYPE == 1)||(TRACE_TYPE == 4)
1969 if (trace_info.current_config->l1_dyn_trace & 1<<L1_DYN_TRACE_CONDENSED_PDTCH)
1970 {
1971 if ((l1pa_l1ps_com.tcr_freq_list.ms_ctrl_dd != 0) ||
1972 ((l1ps.pc_meas_chan_ctrl == TRUE) &&
1973 ((l1s.actual_time.t2 == 3) || (l1s.actual_time.t2 == 11) ||
1974 (l1s.actual_time.t2 == 20))))
1975 trace_info.pdtch_trace.blk_status |= 0x80 >> burst_id;
1976 }
1977 #endif
1978
1979 if(l1ps_dsp_com.pdsp_db_r_ptr->d_burst_nb_gprs == 3)
1980 /*---------------------------------------------------*/
1981 /* Complete PDTCH DL block has been processed by DSP */
1982 /*---------------------------------------------------*/
1983 {
1984
1985 l1pa_l1ps_com.transfer.dl_pwr_ctrl.crc_error = crc_error;
1986 /*
1987 * FreeCalypso TCS211 reconstruction: the following line
1988 * has been taken from the TSM30 source.
1989 */
1990 l1pa_l1ps_com.transfer.dl_pwr_ctrl.assignment_id = l1ps.read_param.assignment_id;
1991
1992 if(l1ps.read_param.pc_meas_chan)
1993 {
1994
1995 // Due to the CWR pipeleine, maca_power_control() has to be called before the
1996 // CTRL of the first PDTCH i.e. in l1ps_ctrl_pdtch(). It means that crc_error,
1997 // radio_freq_tbl[], burst_level[] and bcch_level information are stored on
1998 // burst4 of READ phase to be used on burst4 of CTRL phase.
1999
2000 l1pa_l1ps_com.transfer.dl_pwr_ctrl.bcch_level = (WORD8)0x80;
2001
2002 for(i = 0; i < 4; i++)
2003 {
2004 l1pa_l1ps_com.transfer.dl_pwr_ctrl.radio_freq_tbl[i] = radio_freq_tbl[i];
2005 l1pa_l1ps_com.transfer.dl_pwr_ctrl.burst_level[i] = burst_level[i];
2006 }
2007
2008 }
2009 else
2010 {
2011 // Measures have been performed on BCCH Serving Cell. "burst_level" table is
2012 // not applicable.
2013
2014 // Download measures made on BCCH Serving Cell.
2015 l1pa_l1ps_com.transfer.dl_pwr_ctrl.bcch_level = l1pa_l1ps_com.tcr_freq_list.beacon_meas;
2016
2017 for(i = 0; i < 4; i++)
2018 {
2019 l1pa_l1ps_com.transfer.dl_pwr_ctrl.radio_freq_tbl[i] = radio_freq_tbl[i];
2020 l1pa_l1ps_com.transfer.dl_pwr_ctrl.burst_level[i] = (WORD8)0x80;
2021 }
2022
2023 // Measures on BCCH Serving Cell are only performed every 40ms while
2024 // maca_power_control() is called every 20ms. "beacon_meas" must then
2025 // be set to invalid (0x80) until next Serving Cell measure.
2026 l1pa_l1ps_com.tcr_freq_list.beacon_meas = (WORD8)0x80;
2027
2028 }
2029
2030 #if TESTMODE
2031 // Test mode stats
2032 if (l1_config.TestMode)
2033 {
2034 // Allocate result message.
2035 msg = os_alloc_sig(sizeof(T_TMODE_PDTCH_INFO));
2036 DEBUGMSG(status,NU_ALLOC_ERR)
2037 msg->SignalCode = TMODE_PDTCH_INFO;
2038
2039 ((T_TMODE_PDTCH_INFO *)(msg->SigP))->pm_fullres = tm_pm_fullres; // F26.6
2040 ((T_TMODE_PDTCH_INFO *)(msg->SigP))->snr = tm_snr;
2041 ((T_TMODE_PDTCH_INFO *)(msg->SigP))->toa = tm_toa;
2042 ((T_TMODE_PDTCH_INFO *)(msg->SigP))->angle = tm_angle; // signed
2043 for (i=0;i<8;i++)
2044 ((T_TMODE_PDTCH_INFO *)(msg->SigP))->crc_error_tbl[i] = crc_error_tbl[i];
2045
2046 // send TMODE_TCH_INFO message...
2047 os_send_sig(msg, L1C1_QUEUE);
2048 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
2049
2050 // reset static TM variables for stats collection
2051 tm_pm_fullres = 0;
2052 tm_snr = 0;
2053 tm_toa = 0;
2054 tm_angle = 0;
2055 }
2056 #endif
2057 }
2058
2059 } //end of test "if((en_task) && !(task_param))"
2060
2061 // End of task -> task must become INACTIVE.
2062 // PDTCH can be pipelined and therefore must stay active if
2063 // it has already reentered the flow.
2064 if(burst_id == BURST_4)
2065 {
2066 if(l1s.task_status[task].current_status == RE_ENTERED)
2067 l1s.task_status[task].current_status = ACTIVE;
2068 else
2069 l1s.task_status[task].current_status = INACTIVE;
2070 }
2071
2072 #if 0 /* FreeCalypso TCS211 reconstruction */
2073 l1ddsp_read_iq_dump(task);
2074 #endif
2075 // Flag the use of the MCU/DSP dual page read interface.
2076 // ******************************************************
2077
2078 // Set flag used to change the read page at the end of "l1_synch".
2079 l1s_dsp_com.dsp_r_page_used = TRUE;
2080 }
2081 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
2082 #endif // MOVE_IN_INTERNAL_RAM
2083
2084 /*-------------------------------------------------------*/
2085 /* l1ps_read_pra_result() */
2086 /*-------------------------------------------------------*/
2087 /* Parameters : */
2088 /* Return : */
2089 /* Functionality : */
2090 /*-------------------------------------------------------*/
2091 void l1ps_read_pra_result(UWORD8 task, UWORD8 burst_id)
2092 {
2093 /*--------------------------------------------------------*/
2094 /* READ TRANSMIT TASK RESULTS... */
2095 /*--------------------------------------------------------*/
2096
2097 /*---------------------------------------------------*/
2098 /* Packet Access task. */
2099 /*---------------------------------------------------*/
2100 // Rem: confirmation message is sent at "CTRL" to be able to give FN%42432.
2101 BOOL confirm_flag = TRUE; // Default is: confirmation message is sent.
2102
2103 // Desactivate the PRACH task.
2104 l1s.task_status[task].current_status = INACTIVE;
2105
2106 l1_check_com_mismatch(task);
2107
2108
2109 #if (TRACE_TYPE!=0)
2110 trace_fct(CST_L1PS_READ_PRA, l1pa_l1ps_com.p_idle_param.radio_freq);
2111 #endif
2112
2113 #if FF_L1_IT_DSP_USF
2114 // Check PRACH was controlled
2115 if (l1pa_l1ps_com.pra_info.prach_controlled)
2116 {
2117 #endif
2118
2119 // Check USF in case of Dynamic Allocation.
2120 if(l1pa_l1ps_com.pra_info.prach_alloc != FIX_PRACH_ALLOC)
2121 {
2122 API cs_type = l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][0];
2123
2124 if(cs_type != CS_NONE_TYPE)
2125 confirm_flag = FALSE;
2126 }
2127
2128 if (confirm_flag == TRUE)
2129 {
2130 // Send confirmation msg to L1A.
2131 // ******************************
2132 // For ACCESS phase, a confirmation msg is sent to L1A.
2133 xSignalHeaderRec *msg;
2134
2135 // send L1C_RA_DONE to L1A...
2136 msg = os_alloc_sig(sizeof(T_MPHP_RA_CON));
2137 DEBUGMSG(status,NU_ALLOC_ERR)
2138
2139 ((T_MPHP_RA_CON *)(msg->SigP))->fn = l1pa_l1ps_com.pra_info.fn_to_report;
2140 ((T_MPHP_RA_CON *)(msg->SigP))->channel_request_data = l1pa_l1ps_com.pra_info.channel_request_data;
2141 msg->SignalCode = L1P_RA_DONE;
2142
2143 os_send_sig(msg, L1C1_QUEUE);
2144 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
2145
2146 }
2147
2148 // Set flag used to change the read page at the end of "l1_synch".
2149 l1s_dsp_com.dsp_r_page_used = TRUE;
2150
2151 #if FF_L1_IT_DSP_USF
2152 } // if (l1pa_l1ps_com.pra_info.prach_controlled)
2153 #endif
2154 }
2155
2156 /*-------------------------------------------------------*/
2157 /* l1ps_read_poll_result() */
2158 /*-------------------------------------------------------*/
2159 /* Parameters : */
2160 /* Return : */
2161 /* Functionality : */
2162 /*-------------------------------------------------------*/
2163 void l1ps_read_poll_result(UWORD8 task, UWORD8 burst_id)
2164 {
2165 /*--------------------------------------------------------*/
2166 /* READ TRANSMIT TASK RESULTS... */
2167 /*--------------------------------------------------------*/
2168
2169 l1_check_com_mismatch(task);
2170
2171 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5) // in debug trace all reads
2172 trace_fct(CST_L1PS_READ_POLL, l1pa_l1ps_com.p_idle_param.radio_freq);
2173 #endif
2174
2175 /*--------------------------------------------------------*/
2176 /* POLL task (4xPRACH) upon packet queueing notification. */
2177 /*--------------------------------------------------------*/
2178
2179 // Deactivate the PRACH task.
2180 if(burst_id == BURST_4)
2181 {
2182 // POLL is a 'one shot' task --> disable task
2183 l1a_l1s_com.l1s_en_task[task] = TASK_DISABLED;
2184
2185 l1s.task_status[task].current_status = INACTIVE;
2186
2187 #if (TRACE_TYPE==5) // in simulation trace only the latest burst
2188 trace_fct(CST_L1PS_READ_POLL, l1pa_l1ps_com.p_idle_param.radio_freq);
2189 #endif
2190
2191 // Send confirmation msg to L1A.
2192 // ******************************
2193 // For PACKET POLLING, a confirmation msg is sent to L1A.
2194 {
2195 xSignalHeaderRec *msg;
2196
2197 // send L1C_RA_DONE to L1A...
2198 msg = os_alloc_sig(sizeof(T_MPHP_POLLING_IND));
2199 DEBUGMSG(status,NU_ALLOC_ERR)
2200
2201 ((T_MPHP_POLLING_IND *)(msg->SigP))->fn = l1pa_l1ps_com.poll_info.fn_to_report;
2202 msg->SignalCode = L1P_POLL_DONE;
2203
2204 os_send_sig(msg, L1C1_QUEUE);
2205 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
2206 }
2207 }
2208
2209 #if 0 /* FreeCalypso TCS211 reconstruction */
2210 l1ddsp_read_iq_dump(task);
2211 #endif
2212 // Set flag used to change the read page at the end of "l1_synch".
2213 l1s_dsp_com.dsp_r_page_used = TRUE;
2214 }
2215
2216 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
2217 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
2218
2219 /*-------------------------------------------------------*/
2220 /* l1ps_ctrl_snb_dl() */
2221 /*-------------------------------------------------------*/
2222 /* */
2223 /* Description: */
2224 /* ------------ */
2225 /* This function is a "COMPLEX" function used by the L1S */
2226 /* packet serving cell normal burst reading tasks: PNP, */
2227 /* PEP, PALLC. This function is the control function for */
2228 /* reading a normal burst on the packet serving cell. */
2229 /* It programs the DSP and the TPU for reading a */
2230 /* normal burst. This function flags the reading of the */
2231 /* Packet Normal paging burst which flag is used in */
2232 /* measurement manager procedure. */
2233 /* Here below is a summary of the execution: */
2234 /* */
2235 /* - If SEMAPHORE(task) is low. */
2236 /* - Catch ARFCN and set CIPHERING reduced frame */
2237 /* number. */
2238 /* - Traces and debug. */
2239 /* - Programs DSP for required task. */
2240 /* - Programs TPU for required task. */
2241 /* - Flag the reading of a Packet Normal Paging */
2242 /* burst. */
2243 /* - Flag DSP and TPU programmation. */
2244 /* */
2245 /* Input parameters: */
2246 /* ----------------- */
2247 /* "l1a_l1s_com.task_param" */
2248 /* task semaphore bit register. Used to skip */
2249 /* the body of this function if L1A has changed or */
2250 /* is changing some of the task parameters. */
2251 /* */
2252 /* "task" */
2253 /* PNP, Packet Normal paging reading task. */
2254 /* PEP, Packet Extended paging reading task. */
2255 /* PALLC, All Packet serving cell PCCCH reading task. */
2256 /* */
2257 /* "burst_id" */
2258 /* BURST_1, 1st burst of the task. */
2259 /* BURST_2, 2nd burst of the task. */
2260 /* BURST_3, 3rd burst of the task. */
2261 /* BURST_4, 4th burst of the task. */
2262 /* */
2263 /* Input parameters from globals: */
2264 /* ------------------------------ */
2265 /* "l1a_l1s_com.Scell_info" */
2266 /* Serving cell information structure. */
2267 /* .radio_freq, serving cell beacon frequency. */
2268 /* */
2269 /* "l1s.afc" */
2270 /* current AFC value to be applied for the given task. */
2271 /* */
2272 /* "l1s.tpu_offset" */
2273 /* value for the TPU SYNCHRO and OFFSET registers */
2274 /* for current serving cell setting. It is used here */
2275 /* to refresh the TPU SYNCHRO and OFFSET registers */
2276 /* with a corrected (time tracking of the serving) */
2277 /* value prior to reading a serving cell normal burst. */
2278 /* */
2279 /* Modified parameters from globals: */
2280 /* --------------------------------- */
2281 /* "pnp_ctrl" */
2282 /* Flag set when a packet normal paging burst reading */
2283 /* is controled. This flag is used by the packet */
2284 /* measurement manager procedure, at the end of L1S, */
2285 /* in order to scheduling the neighbor cell */
2286 /* measurements. */
2287 /* -> set to 1. */
2288 /* */
2289 /* */
2290 /* "l1s.tpu_ctrl_reg" */
2291 /* bit register used to know at the end of L1S if */
2292 /* something has been programmed on the MCU/TPU com. */
2293 /* This is used mainly to swap then the com. page at */
2294 /* the end of a control frame. */
2295 /* -> set CTRL_RX bit in the register. */
2296 /* */
2297 /* "l1s.dsp_ctrl_reg" */
2298 /* bit register used to know at the end of L1S if */
2299 /* something has been programmed on the MCU/DSP com. */
2300 /* This is used mainly to swap then the com. page at */
2301 /* the end of a control frame. */
2302 /* -> set CTRL_RX bit in the register. */
2303 /* */
2304 /*-------------------------------------------------------*/
2305 void l1ps_ctrl_snb_dl(UWORD8 task, UWORD8 burst_id)
2306 {
2307 UWORD16 Scell_radio_freq;
2308 UWORD8 tsc;
2309 WORD8 agc;
2310 UWORD8 lna_off;
2311 UWORD8 adc_active = INACTIVE;
2312 #if (RF_FAM == 61)
2313 UWORD16 dco_algo_ctl_nb = 0;
2314 UWORD8 if_ctl = 0;
2315 UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS;
2316 // By default we choose the hardware filter
2317 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
2318 #endif
2319
2320 #if (NEW_SNR_THRESHOLD == 1)
2321 UWORD8 saic_flag = 0;
2322 #endif /* NEW_SNR_THRESHOLD */
2323
2324
2325 #if (FF_L1_FAST_DECODING == 1)
2326 BOOL fast_decoding_authorized = FALSE;
2327
2328 if ( (burst_id == BURST_1) && (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_FORBIDDEN) )
2329 {
2330 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_NONE;
2331 }
2332
2333 fast_decoding_authorized = l1s_check_fast_decoding_authorized(task);
2334
2335 if ( fast_decoding_authorized && l1s_check_deferred_control(task,burst_id) )
2336 {
2337 /* Control is deferred until the upcoming fast decoding IT */
2338 return;
2339 } /* if (fast_decoding_authorized)*/
2340
2341 /* In all other cases, control must be performed now. */
2342 #endif /* FF_L1_FAST_DECODING == 1 */
2343
2344 if(!(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
2345 // Check the task semaphore. The control body is executed only
2346 // when the task semaphore is 0. This semaphore can be set to
2347 // 1 whenever L1A makes some changes to the task parameters.
2348 {
2349 Scell_radio_freq = l1a_l1s_com.Scell_info.radio_freq;
2350
2351 // Catch training sequence code from serving cell BCC (part of BSIC).
2352 tsc = l1pa_l1ps_com.pccch.packet_chn_desc.tsc;
2353
2354 // Packet PAGC Algorithm
2355 // **********************
2356
2357 // for PCCCH serving blocks (PPCH, PEPCH, all PCCCH) we use
2358 // PAGC algorithm. Reference is serving cell.
2359 l1pctl_pagc_ctrl(&agc, &lna_off, l1pa_l1ps_com.p_idle_param.radio_freq,TRUE);
2360
2361 #if(RF_FAM == 61) // Locosto DCO
2362 cust_get_if_dco_ctl_algo(&dco_algo_ctl_nb, &if_ctl, (UWORD8) L1_IL_VALID ,
2363 l1a_l1s_com.Scell_used_IL.input_level,
2364 l1pa_l1ps_com.p_idle_param.radio_freq, if_threshold);
2365 l1ddsp_load_dco_ctl_algo_nb(dco_algo_ctl_nb);
2366 #endif
2367
2368 #if (L1_SAIC != 0)
2369 // If SAIC is enabled, call the low level SAIC control function
2370 // NOTE: l1a_l1s_com.Scell_used_IL.input_level is updated within
2371 // the function l1pctl_pagc_ctrl
2372 csf_filter_choice = l1ctl_saic(l1a_l1s_com.Scell_used_IL.input_level,l1a_l1s_com.mode
2373 #if (NEW_SNR_THRESHOLD == 1)
2374 ,task
2375 ,&saic_flag
2376 #endif
2377 );
2378 #endif
2379
2380 // Debug.
2381 // ******************
2382
2383 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
2384 #if (FF_L1_FAST_DECODING == 1)
2385 l1ddsp_load_fast_dec_task(task,burst_id);
2386 #endif
2387
2388 // Programs DSP Rx Packet Idle burst, still on Timeslot number = 0
2389 // due to previous synchro.
2390 #if FF_L1_IT_DSP_USF
2391 {
2392 BOOL usf_it = FALSE;
2393
2394 // Force IT USF interrupt during PCCCH reorg for Fast USF usage during
2395 // Packet Access. Switch to PA could happen any time during PCCCH reorg.
2396 // Only relevant for RBN%3 = 0 and 1
2397 if (l1a_l1s_com.l1s_en_task[PALLC] == TASK_ENABLED)
2398 {
2399 if (/*(l1s.next_time.fn_mod13 >= 0) && omaps00090550*/(l1s.next_time.fn_mod13 <= 7))
2400 usf_it = TRUE;
2401 }
2402
2403 l1pddsp_idle_rx_nb(burst_id, tsc, l1pa_l1ps_com.p_idle_param.radio_freq, 0, FALSE, usf_it);
2404 }
2405 #else
2406 l1pddsp_idle_rx_nb(burst_id, tsc, l1pa_l1ps_com.p_idle_param.radio_freq, 0, FALSE);
2407 #endif
2408
2409 // ADC measurement
2410 // ***************
2411 // check if during the 1st burst of the bloc an ADC measurement must be performed
2412 if ((burst_id == BURST_1) && (task == PNP))
2413 {
2414 if (l1a_l1s_com.l1s_en_task[PALLC] == TASK_DISABLED) // no reorg mode
2415 {
2416 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING) // perform ADC only one time
2417 {
2418 adc_active = ACTIVE;
2419 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle
2420 }
2421 else
2422 {
2423 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING) // perform ADC on each "period" x bloc
2424 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period
2425 {
2426 adc_active = ACTIVE;
2427 l1a_l1s_com.adc_cpt = 0;
2428 }
2429 }
2430 }
2431 else // ADC measurement in reorg mode
2432 {
2433 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING_REORG) // perform ADC only one time
2434 {
2435 adc_active = ACTIVE;
2436 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle
2437 }
2438 else
2439 {
2440 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING_REORG) // perform ADC on each "period" x bloc
2441 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period
2442 {
2443 adc_active = ACTIVE;
2444 l1a_l1s_com.adc_cpt = 0;
2445 }
2446 }
2447 }
2448 }
2449
2450 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
2451 trace_fct(CST_L1PS_CTRL_SNB_DL, -1);
2452 #endif
2453
2454 // Programs TPU for required task.
2455 // ********************************
2456
2457 // update the TPU with the new TOA if necessary
2458 l1ctl_update_TPU_with_toa();
2459
2460 // tpu pgm...
2461 l1dtpu_serv_rx_nb(l1pa_l1ps_com.p_idle_param.radio_freq,
2462 agc,
2463 lna_off,
2464 l1s.tpu_offset,
2465 l1s.tpu_offset,
2466 FALSE,adc_active
2467 #if (RF_FAM == 61)
2468 ,csf_filter_choice
2469 ,if_ctl
2470 #endif
2471 #if (NEW_SNR_THRESHOLD == 1)
2472 ,saic_flag
2473 #endif /* NEW_SNR_THRESHOLD */
2474 );
2475
2476 // Increment tpu window identifier.
2477 l1s.tpu_win += (l1_config.params.rx_synth_load_split + RX_LOAD);
2478 }
2479
2480 // Flag the reading of a Normal Packet Paging burst.
2481 // *************************************************
2482
2483 // Set PNP controlled flag, used in l1s_meas_manager() to generate measurement only
2484 // if we are not receiving a PPCH.
2485 if((task == PNP) || (task == PEP) || (task == PALLC))
2486 l1pa_l1ps_com.cr_freq_list.pnp_ctrl = burst_id + 1;
2487
2488
2489 // Flag DSP and TPU programmation.
2490 // ********************************
2491
2492 // Set "CTRL_RX" flag in the controle flag register.
2493 l1s.tpu_ctrl_reg |= CTRL_RX;
2494 l1s.dsp_ctrl_reg |= CTRL_RX;
2495
2496 } // end of procedure
2497
2498 /*-------------------------------------------------------*/
2499 /* l1ps_read_nb_dl() */
2500 /*-------------------------------------------------------*/
2501 /* */
2502 /* Description: */
2503 /* ------------ */
2504 /* This function is a "COMPLEX" function used by the L1S */
2505 /* tasks: PNP,PEP,PALLC. */
2506 /* */
2507 /* Here is a summary of the execution: */
2508 /* */
2509 /* - If SEMAPHORE(task) is low and task still enabled. */
2510 /* - Traces and debug. */
2511 /* - Read control results and feed control algo. */
2512 /* - Read DL DATA block from MCU/DSP interface. */
2513 /* - Disactivate task. */
2514 /* - Flag the use of the MCU/DSP dual page read */
2515 /* interface. */
2516 /* */
2517 /* Input parameters: */
2518 /* ----------------- */
2519 /* "task" */
2520 /* PNP, Packet Normal paging reading task. */
2521 /* PEP, Packet Extended paging reading task. */
2522 /* PALLC, All packet serving cell PCCCH reading task. */
2523 /* */
2524 /* "burst_id" */
2525 /* BURST_1, 1st burst of the task. */
2526 /* BURST_2, 2nd burst of the task. */
2527 /* BURST_3, 3rd burst of the task. */
2528 /* BURST_4, 4th burst of the task. */
2529 /* */
2530 /* Input parameters from globals: */
2531 /* ------------------------------ */
2532 /* "l1pa_l1ps_com.task_param[NBR_DL_L1S_TASKS]" */
2533 /* packet task semaphore table. Used to skip */
2534 /* the body of this function if L1A has changed or */
2535 /* is changing some of the task parameters. */
2536 /* */
2537 /* "l1a_l1s_com.l1s_en_task[NBR_DL_L1S_TASKS]" */
2538 /* L1S task enable. */
2539 /* */
2540 /* Modified parameters from globals: */
2541 /* --------------------------------- */
2542 /* "l1s.task_status[task].current_status" */
2543 /* current task status. It must be reset (INACTIVE) */
2544 /* when the task is completed. */
2545 /* -> disactivate task. */
2546 /* */
2547 /* "l1s_dsp_com.dsp_r_page_used" */
2548 /* Flag used by the function which closes L1S */
2549 /* execution ("l1s_end_manager()") to know if the */
2550 /* MCU/DSP read page must be switched. */
2551 /* -> Set to 1. */
2552 /* */
2553 /* Use of MCU/DSP interface: */
2554 /* ------------------------- */
2555 /* "l1s_dsp_com.dsp_ndb_ptr" */
2556 /* pointer to the non double buffered part (NDB) of */
2557 /* the MCU/DSP interface. This part is R/W for both */
2558 /* DSP and MCU. */
2559 /* */
2560 /* "l1s_dsp_com.dsp_db_r_ptr" */
2561 /* pointer to the double buffered part (DB) of the */
2562 /* MCU/DSP interface. This pointer points to the READ */
2563 /* page. */
2564 /* */
2565 /*-------------------------------------------------------*/
2566 void l1ps_read_nb_dl(UWORD8 task, UWORD8 burst_id)
2567 {
2568 UWORD32 toa=0; //omaps00090550
2569 UWORD32 pm=0; //omaps00090550;
2570 UWORD32 angle =0; //omaps00090550
2571 UWORD32 snr =0; //omaps00090550
2572 BOOL en_task;
2573 BOOL task_param;
2574 UWORD16 scell_radio_freq;
2575 static UWORD16 pwr_level;
2576
2577 #if (FF_L1_FAST_DECODING == 1)
2578 UWORD8 skipped_bursts = 0;
2579 BOOL fast_decoding_authorized = l1s_check_fast_decoding_authorized(task);
2580 BOOL fast_decoded = (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_COMPLETE);
2581 if (fast_decoded)
2582 {
2583 skipped_bursts = BURST_4 - burst_id;
2584 }
2585 #endif /* if (FF_L1_FAST_DECODING == 1) */
2586
2587 /*--------------------------------------------------------*/
2588 /* READ SERVING CELL RECEIVE TASK RESULTS... */
2589 /*--------------------------------------------------------*/
2590 /* Rem: only a partial result is present in the mcu<-dsp */
2591 /* communication buffer. The DATA BLOCK content itself is */
2592 /* in the last comm. (BURST_4) */
2593 /*--------------------------------------------------------*/
2594 // Get "enable" task flag and "synchro semaphore" for current task.
2595 en_task = l1a_l1s_com.l1s_en_task[task];
2596 task_param = l1a_l1s_com.task_param[task];
2597
2598 if((en_task) && !(task_param))
2599 // Check the task semaphore and the task enable bit. The reading
2600 // task body is executed only when the task semaphore is 0 and the
2601 // task is still enabled.
2602 // The semaphore can be set to 1 whenever L1A makes some changes
2603 // to the task parameters. The task can be disabled by L1A.
2604 {
2605 // Traces and debug.
2606 // ******************
2607 l1_check_com_mismatch(task);
2608
2609 // Read control results and feed control algorithms.
2610 // **************************************************
2611 if ((task != PBCCHN_TRAN) && (task != PBCCHN_IDLE))
2612 {
2613 // From the fact that PBCCHS can be read in CS mode,
2614 // Idle mode and Packet Idle mode, a check on the current active DSP scheduler mode
2615 // has to be performed.
2616 // Read control information.
2617 // We keep compatibility with (chipset == 0) imply mask with 0xffff.
2618 // If only (chipset == 2) is used, mask can be removed.
2619 if (l1a_l1s_com.dsp_scheduler_mode == GSM_SCHEDULER)
2620 {
2621 toa = l1s_dsp_com.dsp_db_r_ptr->a_serv_demod[D_TOA] & 0xffff;
2622 pm = (l1s_dsp_com.dsp_db_r_ptr->a_serv_demod[D_PM] & 0xffff) >> 5;
2623 angle = l1s_dsp_com.dsp_db_r_ptr->a_serv_demod[D_ANGLE] & 0xffff;
2624 snr = l1s_dsp_com.dsp_db_r_ptr->a_serv_demod[D_SNR] & 0xffff;
2625 }
2626 else
2627 {
2628 toa = l1ps_dsp_com.pdsp_db_r_ptr->a_burst_toa_gprs[0] & 0xffff;
2629 pm = (l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[0] & 0xffff)>>5;
2630 angle = l1ps_dsp_com.pdsp_db_r_ptr->a_burst_angle_gprs[0] & 0xffff;
2631 snr = l1ps_dsp_com.pdsp_db_r_ptr->a_burst_snr_gprs[0] & 0xffff;
2632 }
2633
2634 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
2635 trace_fct(CST_L1PS_READ_NB_DL, -1);
2636 #endif
2637
2638 l1_check_pm_error(pm,task);
2639
2640 // Update AGC: Call PAGC algorithm
2641 l1a_l1s_com.Scell_IL_for_rxlev = l1pctl_pagc_read((UWORD8)pm, l1pa_l1ps_com.p_idle_param.radio_freq_dd);
2642
2643 #if (FF_L1_FAST_DECODING == 1)
2644 if (skipped_bursts>0)
2645 {
2646 l1ctl_pagc_missing_bursts(skipped_bursts);
2647 }
2648 #endif /* if (FF_L1_FAST_DECODING == 1) */
2649
2650 // Update AFC: Call AFC control function (KALMAN filter).
2651 #if AFC_ALGO
2652 {
2653 WORD16 old_afc = l1s.afc;
2654 WORD16 old_count= l1s.afc_frame_count;
2655
2656 scell_radio_freq = l1a_l1s_com.Scell_info.radio_freq;
2657 #if (VCXO_ALGO==0)
2658 l1s.afc = l1ctl_afc(AFC_CLOSED_LOOP, &l1s.afc_frame_count, (WORD16)angle, snr, scell_radio_freq);
2659 #else
2660 l1s.afc = l1ctl_afc(AFC_CLOSED_LOOP, &l1s.afc_frame_count, (WORD16)angle, snr, scell_radio_freq,l1a_l1s_com.mode);
2661 #endif
2662 #if L2_L3_SIMUL
2663 #if (DEBUG_TRACE == BUFFER_TRACE_AFC_OPEN)
2664 buffer_trace (4,(WORD16)angle,old_count,old_afc,l1s.afc);
2665 #endif
2666 #endif
2667 }
2668 #endif
2669
2670 // Feed TOA histogram only when the TOA result is used in the task CTRL function
2671 if (task != PBCCHS)
2672 {
2673 //Feed TOA histogram.
2674 #if (TOA_ALGO != 0)
2675 #if (TOA_ALGO == 2)
2676 if(l1s.toa_var.toa_snr_mask == 0)
2677 #else
2678 if(l1s.toa_snr_mask == 0)
2679 #endif
2680 {
2681 #if (TOA_ALGO == 2)
2682 UWORD32 snr_temp;
2683 snr_temp = (l1a_l1s_com.Scell_IL_for_rxlev < IL_FOR_RXLEV_SNR) ? snr: 0;
2684 l1s.toa_var.toa_shift = l1ctl_toa(TOA_RUN, l1a_l1s_com.mode, snr_temp, toa);
2685 #else
2686 /* FreeCalypso TCS211 reconstruction */
2687 if (l1a_l1s_com.Scell_IL_for_rxlev < IL_FOR_RXLEV_SNR)
2688 {
2689 l1s.toa_shift = l1ctl_toa(TOA_RUN, l1a_l1s_com.mode, snr, toa,
2690 &l1s.toa_update,
2691 &l1s.toa_period_count
2692 #if (FF_L1_FAST_DECODING == 1)
2693 ,0
2694 #endif
2695 );
2696 }
2697 else
2698 {
2699 l1s.toa_shift = l1ctl_toa(TOA_RUN, l1a_l1s_com.mode, 0, toa,
2700 &l1s.toa_update,
2701 &l1s.toa_period_count
2702 #if (FF_L1_FAST_DECODING == 1)
2703 ,0
2704 #endif
2705 );
2706 }
2707 #endif
2708 }
2709 #endif
2710 }
2711 }
2712
2713 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
2714 RTTL1_FILL_DL_BURST(angle, snr, l1s.afc, task, pm, toa, l1a_l1s_com.Scell_IL_for_rxlev + l1a_l1s_com.Scell_info.pb)
2715 #endif
2716 #if 0 //(TRACE_TYPE == 1) || (TRACE_TYPE == 4) // TCS211 reconstruction
2717 l1_trace_burst_param(angle, snr, l1s.afc, task, pm, toa, l1a_l1s_com.Scell_IL_for_rxlev + l1a_l1s_com.Scell_info.pb);
2718 #endif
2719 #if (BURST_PARAM_LOG_ENABLE == 1)
2720 l1_log_burst_param(angle, snr, l1s.afc, task, pm, toa, l1a_l1s_com.Scell_IL_for_rxlev + l1a_l1s_com.Scell_info.pb);
2721 #endif
2722 // compute the Data bloc Power.
2723 // ******************************
2724 if(burst_id == BURST_1)
2725 pwr_level = 0;
2726
2727 // add the burst power
2728 pwr_level += l1a_l1s_com.Scell_IL_for_rxlev;
2729
2730
2731 // Read downlink DATA block from MCU/DSP interface.
2732 // *************************************************
2733 #if (FF_L1_FAST_DECODING == 1)
2734 /* Perform the reporting if
2735 - Burst is the 4th one (whether CRC is ok or not)
2736 - Fast decoding enabled and CRC already ok
2737 */
2738 if ( (burst_id == BURST_4) || fast_decoded )
2739 #else /* #if (FF_L1_FAST_DECODING == 1) */
2740 if(burst_id == BURST_4)
2741 #endif /* FF_L1_FAST_DECODING */
2742 {
2743 #if (TRACE_TYPE==2 ) || (TRACE_TYPE==3)
2744 uart_trace(task);
2745 #endif
2746 #if (FF_L1_FAST_DECODING == 1)
2747 /* Data power block = pwr_level / (nb of bursts)*/
2748 pwr_level = pwr_level / (burst_id + 1);
2749 #else /* #if (FF_L1_FAST_DECODING == 1) */
2750 // the data power bloc = pwr_level/4.
2751 pwr_level = pwr_level >> 2;
2752 #endif /* #if (FF_L1_FAST_DECODING == 1) #else*/
2753
2754 // Read L3 frame block and send msg to L1A.
2755 #if (FF_L1_FAST_DECODING == 1)
2756 if(!fast_decoding_authorized)
2757 {
2758 /* When fast decoding wasn't used, burst_id is undefined (for the trace) */
2759 l1a_l1s_com.last_fast_decoding = 0;
2760 }
2761 else
2762 {
2763 l1a_l1s_com.last_fast_decoding = burst_id + 1;
2764 }
2765 #endif /* #if (FF_L1_FAST_DECODING == 1) */
2766
2767 // Read L3 frame block and send msg to L1A.
2768 if (l1a_l1s_com.dsp_scheduler_mode == GSM_SCHEDULER)
2769 l1s_read_l3frm(pwr_level,&(l1s_dsp_com.dsp_ndb_ptr->a_cd[0]), task);
2770 else
2771 l1s_read_l3frm(pwr_level,&(l1ps_dsp_com.pdsp_ndb_ptr->a_dd_gprs[0][0]), task);
2772
2773 } // End if...
2774
2775 } //end of test "if((en_task) && !(task_param))"
2776
2777 // Disactivate task.
2778 // ******************
2779
2780 // End of task -> task must become INACTIVE.
2781 // Rem: some TASKS (PALLC, PNP (with SPLIT > M)) can be pipelined and therefore
2782 // must stay active if they have already reentered the flow.
2783 #if (FF_L1_FAST_DECODING == 1)
2784 /*------------------------------------------------------*/
2785 /* Perform the reporting if */
2786 /* - Burst is the 4th one (whether CRC is ok or not) */
2787 /* - Fast decoding enabled and CRC already ok */
2788 /*------------------------------------------------------*/
2789 if ( (burst_id == BURST_4) || fast_decoded )
2790 #else /* #if (FF_L1_FAST_DECODING == 1) */
2791 if(burst_id == BURST_4)
2792 #endif /* #if (FF_L1_FAST_DECODING == 1) #else*/
2793 {
2794 #if (FF_L1_FAST_DECODING == 1)
2795 if(task == PNP)
2796 {
2797 if (l1a_apihisr_com.fast_decoding.contiguous_decoding == TRUE)
2798 {
2799 /* A new block has started, a new fast API IT is expected */
2800 l1a_apihisr_com.fast_decoding.contiguous_decoding = FALSE;
2801 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_AWAITED;
2802 }
2803 else if(task == l1a_apihisr_com.fast_decoding.task)
2804 {
2805 /* Reset decoding status */
2806 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_NONE;
2807 }
2808 } /*task == PNP */
2809 #endif /* #if (FF_L1_FAST_DECODING == 1) */
2810 if(l1s.task_status[task].current_status == RE_ENTERED)
2811 l1s.task_status[task].current_status = ACTIVE;
2812 else
2813 l1s.task_status[task].current_status = INACTIVE;
2814 #if (FF_L1_FAST_DECODING == 1)
2815 if (burst_id != BURST_4)
2816 {
2817 l1s_clean_mftab(task, burst_id + 3);
2818 if(l1s.frame_count == (4 -burst_id))
2819 {
2820 l1s.frame_count = 1;
2821 }
2822 }
2823 #endif /* #if (FF_L1_FAST_DECODING == 1) */
2824 }
2825
2826 #if 0 /* FreeCalypso TCS211 reconstruction */
2827 l1ddsp_read_iq_dump(task);
2828 #endif
2829 // Flag the use of the MCU/DSP dual page read interface.
2830 // ******************************************************
2831
2832 // Set flag used to change the read page at the end of "l1_synch".
2833 l1s_dsp_com.dsp_r_page_used = TRUE;
2834
2835 } // end of procedure
2836
2837 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END // KEEP IN EXTERNAL MEM otherwise
2838 #endif
2839 /*-------------------------------------------------------*/
2840 /* l1ps_ctrl_pbcch() */
2841 /*-------------------------------------------------------*/
2842 /* */
2843 /* Description: */
2844 /* ------------ */
2845 /* This function is a "COMPLEX" function used by the L1S */
2846 /* tasks: neighbor cell PBCCH. */
2847 /* This function is the control function */
2848 /* for reading a PBCCH burst on the neighbor cell. */
2849 /* This control function: */
2850 /* a) shifts the OFFSET register to match the normal */
2851 /* burst received task with the PBCCH timeslot number.*/
2852 /* */
2853 /* b) programs a normal burst reading and restores the */
2854 /* OFFSET to the serving cell timeslot. On the last */
2855 /* control (4th burst), the SYNCHRO/OFFSET registers */
2856 /* are shifted back to the normal idle mode PCCH */
2857 /* reading setting. Here is a summary of the */
2858 /* execution: */
2859 /* */
2860 /* - If SEMAPHORE(task) is low. */
2861 /* - Traces and debug. */
2862 /* - Programs DSP for PBCCH task, reading 1 burst. */
2863 /* - Programs TPU for PBCCH task, reading 1 burst. */
2864 /* - Shift TPU SYNCHRO/OFFSET registers back to the */
2865 /* PACKET PAGING TASK timeslot. */
2866 /* - Flag DSP and TPU programmation. */
2867 /* */
2868 /* Input parameters: */
2869 /* ----------------- */
2870 /* "task" */
2871 /* PBCCH_TRA or PBCCH_IDLE or PBCCHS */
2872 /* Serving Cell PBCCH reading task. */
2873 /* */
2874 /* Input parameters from globals: */
2875 /* ------------------------------ */
2876 /* "l1pa_l1ps_com.pbcch " */
2877 /* Neigh/serv Cell PBCCH description structure. */
2878 /* */
2879 /* "l1a_l1s_com.Scell_info.radio_freq" */
2880 /* BSIC of the serving cell. It is used here to pass */
2881 /* the training sequence number (part of BSIC) to the */
2882 /* DSP. */
2883 /* */
2884 /* "l1a_l1s_com.offset_tn0" */
2885 /* value to load in the OFFSET register to shift then */
2886 /* any receive task to the timeslot 0 of the neighbor */
2887 /* cell or PBCCH timeslot number . */
2888 /* */
2889 /* "l1s.tpu_offset" */
2890 /* value for the TPU SYNCHRO and OFFSET registers */
2891 /* for current serving cell setting. It is used here */
2892 /* at the end of the PBCCH task controls to restore */
2893 /* the SYNCHRO/OFFSET registers to the normal setting */
2894 /* in idle mode. */
2895 /* */
2896 /* Modified parameters from globals: */
2897 /* --------------------------------- */
2898 /* "l1s.actual_time, l1s.next_time" */
2899 /* frame number and derived numbers for current frame */
2900 /* and next frame. */
2901 /* -> update to cope with side effect due to synchro. */
2902 /* changes/restores. */
2903 /* */
2904 /* "l1s.tpu_ctrl_reg" */
2905 /* bit register used to know at the end of L1S if */
2906 /* something has been programmed on the MCU/TPU com. */
2907 /* This is used mainly to swap then the com. page at */
2908 /* the end of a control frame. */
2909 /* -> set CTRL_RX bit in the register. */
2910 /* */
2911 /* "l1s.dsp_ctrl_reg" */
2912 /* bit register used to know at the end of L1S if */
2913 /* something has been programmed on the MCU/DSP com. */
2914 /* This is used mainly to swap then the com. page at */
2915 /* the end of a control frame. */
2916 /* -> set CTRL_RX bit in the register. */
2917 /* */
2918 /*-------------------------------------------------------*/
2919 void l1ps_ctrl_pbcch(UWORD8 task, UWORD8 burst_id)
2920 {
2921 UWORD16 rx_radio_freq;
2922 UWORD32 offset_pbcch;
2923 WORD8 agc;
2924 UWORD8 lna_off;
2925 UWORD32 dsp_task;
2926 UWORD8 tsc;
2927 UWORD8 serving_cell;
2928 #if (RF_FAM == 61)
2929 UWORD16 dco_algo_ctl_nb=0;
2930 UWORD8 if_ctl = 0;
2931 UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS;
2932 // By default we choose the hardware filter
2933 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
2934 #endif
2935 #if (NEW_SNR_THRESHOLD == 1)
2936 UWORD8 saic_flag=0;
2937 #endif /* NEW_SNR_THRESHOLD */
2938 static WORD32 new_tpu_offset;
2939 static BOOL change_synchro;
2940
2941 #define PbcchS l1pa_l1ps_com.pbcchs
2942 #define PbcchN l1pa_l1ps_com.pbcchn
2943
2944 #if (CODE_VERSION == SIMULATION)
2945 UWORD32 tpu_w_page;
2946
2947 if (hw.tpu_r_page==0)
2948 tpu_w_page=1;
2949 else
2950 tpu_w_page=0;
2951
2952 hw.rx_id[tpu_w_page][0]=0;
2953 hw.num_rx[tpu_w_page][0]=1;
2954 hw.rx_group_id[tpu_w_page]=1;
2955 #endif
2956
2957 if (task == PBCCHS)
2958 {
2959 tsc = PbcchS.packet_chn_desc.tsc;
2960 offset_pbcch = (PbcchS.tn_pbcch * TN_WIDTH);
2961 serving_cell = TRUE;
2962 }
2963 else
2964 {
2965 tsc = PbcchN.packet_chn_desc.tsc;
2966 offset_pbcch = PbcchN.time_alignmt;
2967 serving_cell = FALSE;
2968 }
2969
2970 if((l1a_l1s_com.l1s_en_task[task] == TASK_ENABLED) &&
2971 !(l1a_l1s_com.task_param[task] == SEMAPHORE_SET))
2972 // Check the task semaphore. The control body is executed only
2973 // when the task semaphore is 0. This semaphore can be set to
2974 // 1 whenever L1A makes some changes to the task parameters.
2975 {
2976 // Get ARFCN to be used for current control. Output of the hopping algorithm.
2977 rx_radio_freq = l1pa_l1ps_com.p_idle_param.radio_freq;
2978
2979 // Traces and debug.
2980 // ******************
2981
2982 #if (TRACE_TYPE==5) && FLOWCHART
2983 trace_flowchart_dsp_tpu(dltsk_trace[task].name);
2984 #endif
2985
2986 #if (TRACE_TYPE!=0)
2987 if (task == PBCCHS)
2988 trace_fct(CST_L1PS_CTRL_PBCCHS, l1a_l1s_com.Scell_info.radio_freq);
2989 else
2990 trace_fct(CST_L1PS_CTRL_PBCCHN, PbcchN.bcch_carrier);
2991 #endif
2992
2993 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
2994
2995 // Programs DSP for PBCCHN task according to the DSP scheduler used
2996 // *****************************************************************
2997 switch(l1a_l1s_com.dsp_scheduler_mode)
2998 {
2999 // dsp pgm is made using GSM scheduler...
3000 case GSM_SCHEDULER:
3001 dsp_task = l1s_swap_iq_dl(rx_radio_freq, task);
3002
3003 // dsp pgm...
3004 l1ddsp_load_rx_task(dsp_task,burst_id,tsc);
3005 break;
3006
3007 // dsp pgm is made using GPRS scheduler...
3008 case GPRS_SCHEDULER:
3009 #if FF_L1_IT_DSP_USF
3010 l1pddsp_idle_rx_nb(burst_id,tsc,rx_radio_freq,0,FALSE,FALSE);
3011 #else
3012 l1pddsp_idle_rx_nb(burst_id,tsc,rx_radio_freq,0,FALSE);
3013 #endif
3014 break;
3015 }
3016
3017 // Check if "Synchro" change is needed.
3018 // *************************************
3019 // If so the synchro is changed by 4 timeslots.
3020 if(burst_id == BURST_1)
3021 {
3022 if (task == PBCCHS)
3023 change_synchro = PbcchS.change_synchro;
3024 else
3025 change_synchro = PbcchN.change_synchro;
3026
3027 if(change_synchro)
3028 {
3029 // compute TPU offset for "current timeslot + 4 timeslot"
3030 new_tpu_offset = l1s.tpu_offset + (4 * TN_WIDTH);
3031
3032 if(new_tpu_offset >= TPU_CLOCK_RANGE)
3033 new_tpu_offset -= TPU_CLOCK_RANGE;
3034
3035 // Slide synchro to match current timeslot + 4 timeslot.
3036 l1dmacro_synchro(SWITCH_TIME, new_tpu_offset);
3037 }
3038 else
3039 {
3040 new_tpu_offset = l1s.tpu_offset;
3041 }
3042 }
3043
3044 // TPU pgm...
3045 //-----------
3046 offset_pbcch += new_tpu_offset;
3047 if (offset_pbcch >= TPU_CLOCK_RANGE)
3048 offset_pbcch -= TPU_CLOCK_RANGE;
3049
3050 // add for debug TPU simu
3051 #if (CODE_VERSION == SIMULATION)
3052 if (task == PBCCHS) // PBCCH serving, compute Ts related to the L1 synchro on the serving
3053 hw.rx_id[tpu_w_page][0]=((TPU_CLOCK_RANGE-new_tpu_offset+offset_pbcch)%TPU_CLOCK_RANGE)/TN_WIDTH;
3054 else // PBCCH Neighbor -> special value for PBCCHN detection in the DSP task
3055 hw.rx_id[tpu_w_page][0]=10;
3056 #endif
3057
3058 // agc is set with the input_level computed from PAGC algo
3059 l1pctl_pagc_ctrl(&agc, &lna_off, rx_radio_freq, serving_cell);
3060
3061 #if(RF_FAM == 61) // Locosto DCO
3062 cust_get_if_dco_ctl_algo(&dco_algo_ctl_nb, &if_ctl, (UWORD8) L1_IL_VALID ,
3063 l1a_l1s_com.Scell_used_IL.input_level , rx_radio_freq, if_threshold);
3064 l1ddsp_load_dco_ctl_algo_nb(dco_algo_ctl_nb);
3065 #endif
3066
3067 #if (L1_SAIC != 0)
3068 // If SAIC is enabled, call the low level SAIC control function
3069 // NOTE: l1a_l1s_com.Scell_used_IL.input_level is updated within
3070 // l1pctl_pagc_ctrl
3071 if(task == PBCCHS)
3072 {
3073 // Call SAIC only for PBCCHS, not for PBCCHN_TRAN or PBCCHN_IDLE
3074 csf_filter_choice = l1ctl_saic(l1a_l1s_com.Scell_used_IL.input_level,l1a_l1s_com.mode
3075 #if (NEW_SNR_THRESHOLD == 1)
3076 ,task
3077 ,&saic_flag
3078 #endif
3079 );
3080 }
3081 #endif
3082
3083 l1dmacro_offset (offset_pbcch, l1_config.params.rx_change_offset_time); // Slide offset to cope with PBCCHN in the new sychro.
3084 l1dmacro_rx_synth(rx_radio_freq); // load SYNTH.
3085 l1dmacro_agc (rx_radio_freq,agc, lna_off
3086 #if(RF_FAM == 61)
3087 ,if_ctl
3088 #endif
3089 ); // load AGC.
3090 #if (L1_MADC_ON == 1)
3091 #if (RF_FAM == 61)
3092 l1dmacro_rx_nb (rx_radio_freq,INACTIVE, csf_filter_choice
3093 #if (NEW_SNR_THRESHOLD == 1)
3094 ,saic_flag
3095 #endif /* NEW_SNR_THRESHOLD */
3096 ); // RX window for NB.
3097 #endif /* RF_FAM == 61*/
3098 #else /* L1_MADC_ON == 1*/
3099 l1dmacro_rx_nb (rx_radio_freq); // RX window for NB.
3100 #endif
3101
3102 if (task == PBCCHS)
3103 {
3104 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
3105 l1ddsp_load_afc(l1s.afc); // Loading the afc value in DB,Flag the presence of a new afc value to send
3106 #endif
3107 #if (RF_FAM == 61)
3108 l1dtpu_load_afc(l1s.afc);
3109 #endif
3110 }
3111 l1dmacro_offset (new_tpu_offset, IMM); // Restore offset.
3112 } // End if(task enabled and semaphore false)
3113
3114 // Remark:
3115 //--------
3116 // When the task is aborted, we must continue to make dummy
3117 // DSP programming to avoid communication mismatch due
3118 // to C/W/R pipelining.
3119
3120 // We must also ensure the Synchro back since synchro change has surely be done
3121 // in the 1st CTRL phase.
3122
3123 // Shift TPU SYNCHRO/OFFSET registers back to the default timeslot (normally PCCCH one).
3124 // **************************************************************************************
3125 // When the PBCCHN or PBCCHS reading control is completed ,
3126 // the SYNCHRO/OFFSET registers are shifted back to the normal idle
3127 // setting used for PCCH reading on the serving cell.
3128 // Check if "Synchro" change was needed.
3129 // If so the synchro is changed to recover normal synchro.
3130 if(burst_id == BURST_4)
3131 {
3132 if(change_synchro)
3133 {
3134 // Slide synchro back to mach current serving timeslot.
3135 l1dmacro_synchro(SWITCH_TIME, l1s.tpu_offset);
3136
3137 // Increment frame number.
3138 l1s.actual_time = l1s.next_time;
3139 l1s.next_time = l1s.next_plus_time;
3140 l1s_increment_time(&(l1s.next_plus_time), 1); // Increment "next_plus time".
3141
3142 l1s.tpu_ctrl_reg |= CTRL_SYCB;
3143 l1s.dsp_ctrl_reg |= CTRL_SYNC;
3144
3145 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
3146 trace_fct(CST_L1S_ADJUST_TIME, -1);
3147 #endif
3148 }
3149 }
3150
3151 // Flag DSP and TPU programmation.
3152 // ********************************
3153
3154 // Set "CTRL_RX" flag in the controle flag register.
3155 l1s.tpu_ctrl_reg |= CTRL_RX;
3156 l1s.dsp_ctrl_reg |= CTRL_RX;
3157
3158 // This task is not compatible with Neigh. Measurement. Store task length
3159 // in "forbid_meas" to indicate when the task will last.
3160 if((burst_id == BURST_1) && (task != PBCCHN_IDLE))
3161 {
3162 // In PBCCHN_IDLE task, l1s.forbid_meas is set by the AGC ctrl
3163 l1s.forbid_meas = TASK_ROM_MFTAB[task].size;
3164 }
3165 }
3166
3167 #if (MOVE_IN_INTERNAL_RAM == 0) // Must be followed by the pragma used to duplicate the funtion in internal RAM
3168 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
3169
3170 /*-------------------------------------------------------*/
3171 /* l1ps_ctrl_ptcch() */
3172 /*-------------------------------------------------------*/
3173 /* */
3174 /* Description: */
3175 /* ------------ */
3176 /* */
3177 /* Input parameters: */
3178 /* ----------------- */
3179 /* */
3180 /* Input parameters from globals: */
3181 /* ------------------------------ */
3182 /* */
3183 /* Modified parameters from globals: */
3184 /* --------------------------------- */
3185 /* */
3186 /*-------------------------------------------------------*/
3187 void l1ps_ctrl_ptcch(UWORD8 param1, UWORD8 param2)
3188 {
3189 UWORD16 radio_freq;
3190 UWORD8 burst_nb;
3191 #if (RF_FAM == 61)
3192 UWORD16 dco_algo_ctl_nb = 0;
3193 UWORD8 if_ctl = 0;
3194 UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS;
3195 #endif
3196 #if (NEW_SNR_THRESHOLD == 1)
3197 UWORD8 saic_flag=0;
3198 #endif /* NEW_SNR_THRESHOLD*/
3199
3200 if(!(l1a_l1s_com.task_param[PTCCH] == SEMAPHORE_SET))
3201 // Check the task semaphore. The control body is executed only
3202 // when the task semaphore is 0. This semaphore can be set to
3203 // 1 whenever L1A makes some changes to the task parameters.
3204 {
3205 WORD8 ts;
3206
3207 radio_freq = l1pa_l1ps_com.transfer.ptcch.radio_freq;
3208
3209 // Traces and debug.
3210 // ******************
3211 #if (TRACE_TYPE!=0)
3212 if(l1pa_l1ps_com.transfer.ptcch.activity && (PTCCH_DL || PTCCH_UL ) == 0) // trace only if a window is programmed.
3213 trace_fct(CST_L1PS_CTRL_PTCCH_EMPTY, radio_freq);
3214 #endif
3215
3216 #if (TRACE_TYPE==5) && FLOWCHART
3217 trace_flowchart_dsp_tpu(dltsk_trace[PTCCH].name);
3218 #endif
3219
3220 l1s_dsp_com.dsp_db_w_ptr->d_debug = (l1s.debug_time + 2) ;
3221
3222 switch (l1s.next_time.fn_mod104)
3223 {
3224 case 12: burst_nb=0; break;
3225 case 38: burst_nb=1; break;
3226 case 64: burst_nb=2; break;
3227 case 90: burst_nb=3; break;
3228 default: burst_nb=0; break;
3229 }
3230
3231 // Compute timeslot number referenced to current camp timeslot.
3232 ts = l1pa_l1ps_com.transfer.aset->packet_ta.ta_tn - l1a_l1s_com.dl_tn;
3233 if(ts < 0) ts += 8;
3234 else if(ts >= 8) ts -= 8;
3235
3236 if(l1pa_l1ps_com.transfer.ptcch.activity & PTCCH_DL)
3237 // PTCCH DL activity bit is set: PTCCH DL programmation is required.
3238 {
3239 #if (TRACE_TYPE!=0)
3240 trace_fct(CST_L1PS_CTRL_PTCCH_DL_BURST0 + burst_nb, radio_freq);
3241 #endif
3242
3243 // Programs DSP for PTCCH/DL.
3244 // ***************************
3245 {
3246 #if FF_L1_IT_DSP_USF
3247 l1pddsp_idle_rx_nb(burst_nb,
3248 l1pa_l1ps_com.transfer.aset->tsc,
3249 radio_freq,
3250 ts,
3251 TRUE,
3252 FALSE);
3253 #else
3254 l1pddsp_idle_rx_nb(burst_nb,
3255 l1pa_l1ps_com.transfer.aset->tsc,
3256 radio_freq,
3257 ts,
3258 TRUE);
3259 #endif
3260 }
3261
3262
3263 // Programs TPU for PTCCH/DL task.
3264 // ********************************
3265 {
3266 WORD8 agc;
3267 UWORD8 lna_off;
3268
3269 // AGC updating
3270 //-------------
3271 l1pctl_pagc_ctrl(&agc, &lna_off, radio_freq,TRUE);
3272
3273 #if(RF_FAM == 61) // Locosto DCO
3274 cust_get_if_dco_ctl_algo(&dco_algo_ctl_nb, &if_ctl, (UWORD8) L1_IL_VALID,
3275 l1a_l1s_com.Scell_used_IL.input_level , radio_freq, if_threshold);
3276 l1ddsp_load_dco_ctl_algo_nb(dco_algo_ctl_nb);
3277 #endif
3278
3279 #if (L1_SAIC != 0)
3280 // If SAIC is enabled, call the low level SAIC control function
3281 // NOTE: l1a_l1s_com.Scell_used_IL.input_level is updated within
3282 // the function l1pctl_pagc_ctrl
3283 l1ctl_saic(l1a_l1s_com.Scell_used_IL.input_level,l1a_l1s_com.mode
3284 #if (NEW_SNR_THRESHOLD == 1)
3285 ,PTCCH
3286 ,&saic_flag
3287 #endif
3288 );
3289 #endif
3290
3291 // Compute timeslot number referenced to current camp timeslot.
3292 // Rem: COULD BE DONE ASYNCHRONOUSLY changing ta_tn definition!!!
3293 ts = l1pa_l1ps_com.transfer.aset->packet_ta.ta_tn - l1a_l1s_com.dl_tn;
3294 if(ts < 0) ts += 8;
3295 else if(ts >= 8) ts -= 8;
3296
3297 // Program RX Normal Burst scenario.
3298 l1pdtpu_serv_rx_nb(radio_freq,
3299 agc,
3300 lna_off,
3301 ts,
3302 l1s.tpu_offset,
3303 1,
3304 1,
3305 TRUE,INACTIVE
3306 #if(RF_FAM == 61)
3307 ,L1_SAIC_HARDWARE_FILTER
3308 ,if_ctl
3309 #endif
3310 #if (NEW_SNR_THRESHOLD == 1)
3311 ,saic_flag
3312 #endif /* NEW_SNR_THRESHOLD */
3313 );
3314
3315 // Set "CTRL_RX" flag in the controle flag registers.
3316 l1s.tpu_ctrl_reg |= CTRL_RX;
3317 l1s.dsp_ctrl_reg |= CTRL_RX;
3318 }
3319 }
3320
3321 if(l1pa_l1ps_com.transfer.ptcch.activity & PTCCH_UL)
3322 // PTCCH UL activity bit is set: PTCCH UL programmation required.
3323 {
3324 UWORD8 adc_active = INACTIVE;
3325
3326 #if (TRACE_TYPE!=0)
3327 trace_fct(CST_L1PS_CTRL_PTCCH_UL, radio_freq);
3328 #endif
3329
3330 // Programs DSP for PTCCH/UL.
3331 // ***************************
3332 {
3333 UWORD8 cs_type;
3334 UWORD16 ptcch_ul_data;
3335
3336 // Access burst type ?
3337 if (l1pa_l1ps_com.access_burst_type == ACC_BURST_8)
3338 {
3339 // PRACH 8 bits: data = (0111 1111)b
3340 cs_type = CS_PAB8_TYPE;
3341 ptcch_ul_data = 0x7F;
3342 }
3343 else
3344 {
3345 // PRACH 11 bits: data = (111 1111 1111)b
3346 cs_type = CS_PAB11_TYPE;
3347 ptcch_ul_data = 0x7FF;
3348 }
3349
3350 // "As" IDLE POLLING PRACH dsp control.
3351 l1pddsp_ul_ptcch_data(cs_type,
3352 ptcch_ul_data,
3353 l1a_l1s_com.Scell_info.bsic,
3354 radio_freq,
3355 ts+3);
3356
3357 l1pddsp_idle_prach_power(l1s.applied_txpwr,
3358 radio_freq,
3359 ts+3);
3360 }
3361
3362 // ADC measurement
3363 // ***************
3364 {
3365 // check if during the SACCH burst an ADC measurement must be performed
3366 if (l1a_l1s_com.adc_mode & ADC_NEXT_TRAFFIC_UL) // perform ADC only one time
3367 {
3368 adc_active = ACTIVE;
3369 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_TRAFFIC; // reset in order to have only one ADC measurement in Traffic
3370 }
3371 else
3372 if (l1a_l1s_com.adc_mode & ADC_EACH_TRAFFIC_UL) // perform ADC on each period bloc
3373 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_traffic_period) // wait for the period
3374 {
3375 adc_active = ACTIVE;
3376 l1a_l1s_com.adc_cpt = 0;
3377 }
3378 }
3379 // Programs TPU for PTCCH/UL task.
3380 // ********************************
3381 {
3382 // Program TX RA scenario.
3383 l1pdtpu_serv_tx(radio_freq,
3384 0, // TA=0.
3385 l1s.tpu_offset,
3386 ts+3, // tx_id.
3387 1, // 1 PRACH.
3388 1, // tx_group_id.
3389 0, // No switch NB->RA
3390 1, // Driver called for PRACH Burst.
3391 l1pa_l1ps_com.transfer.ptcch.activity & PTCCH_DL,adc_active);
3392 // Flag RX in same frame as TX
3393 }
3394
3395 // PTCCH/UL has been executed,
3396 // -> PTCCH/DL is then requested for schedule.
3397 // -> PTCCH/UL activity flag must be reset.
3398 l1pa_l1ps_com.transfer.ptcch.request_dl = TRUE;
3399 l1pa_l1ps_com.transfer.ptcch.activity ^= PTCCH_UL;
3400
3401 // Set "CTRL_TX" flag in the controle flag register.
3402 l1s.tpu_ctrl_reg |= CTRL_TX;
3403 l1s.dsp_ctrl_reg |= CTRL_TX;
3404
3405 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
3406 RTTL1_FILL_UL_AB(PTCCH,l1s.applied_txpwr)
3407 #endif
3408
3409 } // End of PTCCH UL programmation
3410 } // End of if(...semaphore...)
3411
3412 // This task is not compatible with Neigh. Measurement. Store task length
3413 // in "forbid_meas" to indicate when the task will last.
3414 l1s.forbid_meas = TASK_ROM_MFTAB[PTCCH].size;
3415 }
3416 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
3417 #endif // MOVE_IN_INTERNAL_RAM
3418
3419
3420 #if (MOVE_IN_INTERNAL_RAM == 0) // Must be followed by the pragma used to duplicate the funtion in internal RAM
3421 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
3422
3423 /*-------------------------------------------------------*/
3424 /* l1s_read_ptcch() */
3425 /*-------------------------------------------------------*/
3426 /* */
3427 /* Description: */
3428 /* ------------ */
3429 /* */
3430 /* Input parameters: */
3431 /* ----------------- */
3432 /* */
3433 /* Input parameters from globals: */
3434 /* ------------------------------ */
3435 /* */
3436 /* Modified parameters from globals: */
3437 /* --------------------------------- */
3438 /* */
3439 /*-------------------------------------------------------*/
3440 void l1ps_read_ptcch(UWORD8 param1, UWORD8 param2)
3441 {
3442 // Traces and debug.
3443 // ******************
3444
3445 l1_check_com_mismatch(PTCCH);
3446
3447 if(l1pa_l1ps_com.transfer.ptcch.activity & PTCCH_DL)
3448 // PTCCH/DL has been executed,
3449 {
3450 UWORD32 pm;
3451 WORD8 ts;
3452
3453 // Compute timeslot number referenced to current camp timeslot.
3454 ts = l1pa_l1ps_com.transfer.aset->packet_ta.ta_tn - l1a_l1s_com.dl_tn;
3455 if(ts < 0) ts += 8;
3456 else if(ts >= 8) ts -= 8;
3457
3458 #if (TRACE_TYPE!=0)
3459 trace_fct(CST_L1PS_READ_PTCCH_DL, l1pa_l1ps_com.transfer.ptcch.radio_freq);
3460 #endif
3461
3462 // Read control results and feed control algorithms.
3463 // **************************************************
3464
3465 // Read control information.
3466 pm = (l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[ts] & 0xffff) >> 5;
3467 l1_check_pm_error(pm,PTCCH);
3468
3469 if(l1s.actual_time.fn_mod104 == 91)
3470 // Read PTCCH/DL data block from DSP/MCU interface, a_dd_md_gprs[].
3471 {
3472 BOOL crc;
3473 UWORD8 ordered_ta;
3474
3475 crc = (l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[0] & 0x0100) >> 8;
3476
3477 if(!crc)
3478 // Block correct, we extract new TA...
3479 {
3480 UWORD8 word_position = 4+ (l1pa_l1ps_com.transfer.aset->packet_ta.ta_index >> 1);
3481 UWORD8 byte_position = l1pa_l1ps_com.transfer.aset->packet_ta.ta_index & 0x01;
3482
3483 // Download ordered TA...
3484 // IF byte_position
3485 // Upper byte contains TA...
3486 // ELSE
3487 // Lower byte contains TA...
3488 // (see GSM04.04)
3489
3490 ordered_ta = (l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[word_position] >> (8*byte_position)) & 0x7f;
3491
3492 if (ordered_ta < 64)
3493 {
3494 // PTCCH/DL contains a valid TA for MS: update TA
3495 l1pa_l1ps_com.transfer.aset->packet_ta.ta = ordered_ta;
3496
3497 // PTCCH/DL activity bit must reset when new TA has been successfully received.
3498 l1pa_l1ps_com.transfer.ptcch.activity ^= PTCCH_DL;
3499 }
3500 }
3501
3502 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
3503 if (trace_info.current_config->l1_dyn_trace & 1<<L1_DYN_TRACE_DL_PTCCH)
3504 // whatever the value is, trace it
3505 {
3506 Trace_dl_ptcch(ordered_ta,
3507 crc,
3508 l1pa_l1ps_com.transfer.aset->packet_ta.ta_index,
3509 l1pa_l1ps_com.transfer.aset->packet_ta.ta_tn,
3510 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[4],
3511 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[5],
3512 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[6],
3513 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[7],
3514 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[8],
3515 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[9],
3516 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[10],
3517 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[11]);
3518 }
3519 #endif
3520
3521 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
3522 RTTL1_FILL_DL_PTCCH(crc, ordered_ta) // Replace with ordered TA
3523 #endif
3524
3525 // Reset CS type.
3526 l1ps_dsp_com.pdsp_ndb_ptr->a_dd_md_gprs[0] = CS_NONE_TYPE;
3527 }
3528 }
3529 else
3530 {
3531 #if (TRACE_TYPE!=0)
3532 trace_fct(CST_L1PS_READ_PTCCH_UL, l1pa_l1ps_com.transfer.ptcch.radio_freq);
3533 #endif
3534 }
3535
3536 // Set flag used to change the read page at the end of "l1_synch".
3537 l1s_dsp_com.dsp_r_page_used = TRUE;
3538
3539 // End of task -> task must become INACTIVE.
3540 l1s.task_status[PTCCH].current_status = INACTIVE;
3541 }
3542 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
3543 #endif // MOVE_IN_INTERNAL_RAM
3544
3545
3546 #if (MOVE_IN_INTERNAL_RAM == 0) // Must be followed by the pragma used to duplicate the funtion in internal RAM
3547 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
3548
3549 /*-------------------------------------------------------*/
3550 /* l1ps_ctrl_itmeas() */
3551 /*-------------------------------------------------------*/
3552 /* */
3553 /* Description: */
3554 /* ------------ */
3555 /* This function is a "COMPLEX" function used by the L1S */
3556 /* task ITMEAS. */
3557 /* This function is the control function for measuring */
3558 /* the signal strength on several specified timeslots (on*/
3559 /* which it's possible according to the multi-slot class)*/
3560 /* of an indicated carrier. */
3561 /* It programs the DSP and the TPU for doing these */
3562 /* measurements */
3563 /* Here below is a summary of the execution: */
3564 /* */
3565 /* - If SEMAPHORE(task) is low. */
3566 /* - Traces and debug. */
3567 /* - Determines on which timeslots measurements can */
3568 /* be done */
3569 /* - Programs DSP for required task. */
3570 /* - Programs TPU for required task. */
3571 /* - Flag DSP and TPU programmation. */
3572 /* */
3573 /* Input parameters: */
3574 /* ----------------- */
3575 /* */
3576 /* Input parameters from globals: */
3577 /* ------------------------------ */
3578 /* "l1pa_l1ps_com.itmeas" */
3579 /* Interference measurement parameters structure */
3580 /* */
3581 /* "l1a_l1s_com.dl_tn" */
3582 /* Timeslot on which L1 is synchronized */
3583 /* */
3584 /* "l1pa_l1ps_com.transfer.aset->multislot_class" */
3585 /* Multi-slot class in Packet transfer */
3586 /* */
3587 /* Modified parameters from globals: */
3588 /* --------------------------------- */
3589 /* */
3590 /* "l1s.tpu_ctrl_reg" */
3591 /* bit register used to know at the end of L1S if */
3592 /* something has been programmed on the MCU/TPU com. */
3593 /* This is used mainly to swap then the com. page at */
3594 /* the end of a control frame. */
3595 /* -> set CTRL_RX bit in the register. */
3596 /* */
3597 /* "l1s.dsp_ctrl_reg" */
3598 /* bit register used to know at the end of L1S if */
3599 /* something has been programmed on the MCU/DSP com. */
3600 /* This is used mainly to swap then the com. page at */
3601 /* the end of a control frame. */
3602 /* -> set CTRL_RX bit in the register. */
3603 /*-------------------------------------------------------*/
3604 void l1ps_ctrl_itmeas(UWORD8 param1, UWORD8 param2)
3605 {
3606
3607 #if (RF_FAM == 61)
3608 UWORD16 dco_algo_ctl_pw = 0;
3609 UWORD8 if_ctl = 0;
3610 UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS;
3611 UWORD8 ts = 0;
3612 #endif
3613
3614 // Traces and debug.
3615 // ******************
3616
3617 #if (TRACE_TYPE==5)
3618 trace_fct(CST_L1PS_CTRL_ITMEAS, l1pa_l1ps_com.itmeas.radio_freq);
3619 #endif
3620
3621 // Timeslots selection
3622 // ********************
3623
3624 // Packet transfer mode <-> PDTCH task enabled: condition to check !!!!
3625 //---------------------
3626
3627 // Timeslots already selected in l1p_asyn.c
3628
3629 // Packet idle mode
3630 //-----------------
3631 if (l1a_l1s_com.l1s_en_task[PDTCH] == TASK_DISABLED)
3632 {
3633 // If a RX has been programmed on this frame
3634 if (l1s.dsp_ctrl_reg & CTRL_RX)
3635 {
3636 // The pre-processed bitmap with Rx taken into account is taken
3637 l1pa_l1ps_com.itmeas.meas_bitmap = l1pa_l1ps_com.itmeas.idle_tn_rx;
3638 }
3639 else
3640 {
3641 // The pre-processed bitmap without Rx taken into account is taken
3642 l1pa_l1ps_com.itmeas.meas_bitmap = l1pa_l1ps_com.itmeas.idle_tn_no_rx;
3643 }
3644
3645 } // End if 'packet idle mode'
3646
3647 l1pa_l1ps_com.itmeas.dsp_r_page_switch_req = FALSE;
3648
3649 // If some measurements can be done
3650 if (l1pa_l1ps_com.itmeas.meas_bitmap != 0)
3651 {
3652 UWORD8 nbmeas;
3653
3654 // DSP read page switched or not during the ITMEAS read phase ?
3655
3656 if (l1s.dsp_ctrl_reg == NO_CTRL)
3657 {
3658 // A control task hasn't already been done in this frame --> Read page switch
3659 l1pa_l1ps_com.itmeas.dsp_r_page_switch_req = TRUE;
3660 }
3661
3662 // Traces and debug.
3663 // ******************
3664 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
3665 trace_fct(CST_L1PS_CTRL_ITMEAS, l1pa_l1ps_com.itmeas.radio_freq);
3666 #endif
3667
3668
3669 #if(RF_FAM == 61) // Locosto DCO
3670 #if (PWMEAS_IF_MODE_FORCE == 0)
3671 cust_get_if_dco_ctl_algo(&dco_algo_ctl_pw, &if_ctl, (UWORD8) L1_IL_INVALID ,
3672 0, l1pa_l1ps_com.itmeas.radio_freq, if_threshold);
3673 #else
3674 if_ctl = IF_120KHZ_DSP;
3675 dco_algo_ctl_pw = DCO_IF_0KHZ;
3676 #endif
3677
3678
3679
3680 #endif
3681
3682 // Program TPU
3683 // ************
3684 #if (RF_FAM != 61)
3685 nbmeas = l1pdtpu_interf_meas(l1pa_l1ps_com.itmeas.radio_freq,
3686 l1_config.params.high_agc,
3687 0,
3688 l1pa_l1ps_com.itmeas.meas_bitmap,
3689 l1s.tpu_offset,
3690 l1s.tpu_win,
3691 l1a_l1s_com.dl_tn);
3692 #endif
3693
3694 #if (RF_FAM == 61)
3695 nbmeas = l1pdtpu_interf_meas(l1pa_l1ps_com.itmeas.radio_freq,
3696 l1_config.params.high_agc,
3697 0,
3698 l1pa_l1ps_com.itmeas.meas_bitmap,
3699 l1s.tpu_offset,
3700 l1s.tpu_win,
3701 l1a_l1s_com.dl_tn,
3702 if_ctl);
3703 #endif
3704
3705
3706 // Program DSP
3707 // ************
3708
3709 l1pddsp_interf_meas_ctrl(nbmeas);
3710
3711 #if(RF_FAM == 61) // TBD
3712 // Reproduce the DCO control for all the power measurement
3713 dco_algo_ctl_pw = dco_algo_ctl_pw * 0x55; // Replicate ZLZLZLZL
3714 dco_algo_ctl_pw = dco_algo_ctl_pw >> (2*(4 - nbmeas)); // reduce to ZLs of Nbr
3715 if(l1s.tcr_prog_done==1)
3716 {
3717 dco_algo_ctl_pw=((dco_algo_ctl_pw<<2)|(l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_pw&0x3));
3718 }
3719 l1ddsp_load_dco_ctl_algo_pw(dco_algo_ctl_pw);
3720 // of Meas Programmed
3721 #endif
3722 // Flag DSP and TPU programmation.
3723 // ********************************
3724
3725 // Set "CTRL_RX" flag in the controle flag register.
3726 l1s.tpu_ctrl_reg |= CTRL_MS;
3727 l1s.dsp_ctrl_reg |= CTRL_MS;
3728
3729 } // End if 'nbmeas != 0'
3730
3731 // This task is not compatible with Neigh. Measurement. Store task length
3732 // in "forbid_meas" to indicate when the task will last.
3733 // Rem: Only FB51 task starts from this ctrl function.
3734 l1s.forbid_meas = TASK_ROM_MFTAB[ITMEAS].size;
3735 }
3736 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
3737 #endif // MOVE_IN_INTERNAL_RAM
3738
3739
3740 #if (MOVE_IN_INTERNAL_RAM == 0) // Must be followed by the pragma used to duplicate the funtion in internal RAM
3741 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
3742
3743 /*-------------------------------------------------------*/
3744 /* l1ps_read_itmeas() */
3745 /*-------------------------------------------------------*/
3746 /* */
3747 /* Description: */
3748 /* ------------ */
3749 /* */
3750 /* This function is a "COMPLEX" function used for the */
3751 /* L1S ITMEAS task. */
3752 /* */
3753 /* Here is a summary of the execution: */
3754 /* */
3755 /* - If SEMAPHORE(task) is low and task still enabled. */
3756 /* - Traces and debug. */
3757 /* - Read interference measurement results in NDB */
3758 /* - Fill and send reporting message */
3759 /* - Disactivate task. */
3760 /* - Flag the use of the MCU/DSP dual page read */
3761 /* interface if needed. */
3762 /* */
3763 /* Input parameters: */
3764 /* ----------------- */
3765 /* */
3766 /* Input parameters from globals: */
3767 /* ------------------------------ */
3768 /* "l1pa_l1ps_com.itmeas" */
3769 /* Interference measurement parameters structure */
3770 /* */
3771 /* Modified parameters from globals: */
3772 /* --------------------------------- */
3773 /* "l1s.task_status[task].current_status" */
3774 /* current task status. It must be reset (INACTIVE) */
3775 /* when the task is completed. */
3776 /* -> disactivate task. */
3777 /* */
3778 /* "l1s_dsp_com.dsp_r_page_used" */
3779 /* Flag used by the function which closes L1S */
3780 /* execution ("l1s_end_manager()") to know if the */
3781 /* MCU/DSP read page must be switched. */
3782 /* -> Set to 1 only if no other task was controlled */
3783 /* in the same frame as ITMEAS */
3784 /* */
3785 /* Use of MCU/DSP interface: */
3786 /* ------------------------- */
3787 /* "l1s_dsp_com.dsp_ndb_ptr" */
3788 /* pointer to the non double buffered part (NDB) of */
3789 /* the MCU/DSP interface. This part is R/W for both */
3790 /* DSP and MCU. */
3791 /*-------------------------------------------------------*/
3792 void l1ps_read_itmeas(UWORD8 param1, UWORD8 param2)
3793 {
3794 xSignalHeaderRec *msg;
3795 UWORD8 i;
3796 WORD8 delta1_freq, delta2_freq;
3797 UWORD16 g_magic;
3798
3799 if(!(l1a_l1s_com.task_param[ITMEAS]) &&
3800 (l1a_l1s_com.l1s_en_task[ITMEAS]))
3801 {
3802 // Traces and debug.
3803 // ******************
3804
3805 #if (TRACE_TYPE!=0)
3806 trace_fct(CST_L1PS_READ_ITMEAS, l1pa_l1ps_com.itmeas.radio_freq);
3807 #endif
3808
3809 // Allocate result message.
3810 // ************************
3811
3812 msg = os_alloc_sig(sizeof(T_L1P_ITMEAS_IND));
3813 DEBUGMSG(status,NU_ALLOC_ERR)
3814
3815 // Fill msg signal code
3816 msg->SignalCode = L1P_ITMEAS_IND;
3817
3818 // Fill msg contents
3819 // ******************
3820
3821 ((T_L1P_ITMEAS_IND *)(msg->SigP))->fn = l1s.actual_time.fn;
3822 // Report measurement bitmap
3823 ((T_L1P_ITMEAS_IND *)(msg->SigP))->meas_bitmap = l1pa_l1ps_com.itmeas.meas_bitmap;
3824
3825 // Read result from DSP
3826 g_magic = l1ctl_get_g_magic(l1pa_l1ps_com.itmeas.radio_freq);
3827 delta1_freq = l1ctl_encode_delta1(l1pa_l1ps_com.itmeas.radio_freq);
3828 delta2_freq = l1ctl_encode_delta2(l1pa_l1ps_com.itmeas.radio_freq);
3829
3830 for (i = 0; i < 8; i++)
3831 {
3832 UWORD8 pm;
3833 WORD16 IL_for_rxlev;
3834
3835 pm = (l1ps_dsp_com.pdsp_ndb_ptr->a_interf_meas_gprs[i] & 0xffff) >> 5;
3836
3837 // IL processing
3838 if (pm == 0)
3839 {
3840 ((T_L1P_ITMEAS_IND *)(msg->SigP))->rxlev[i] = (WORD8)0x80;
3841 }
3842 else
3843 {
3844 IL_for_rxlev = -(pm - (l1_config.params.high_agc << 1) - g_magic) - delta1_freq - delta2_freq;
3845
3846
3847 ((T_L1P_ITMEAS_IND *)(msg->SigP))->rxlev[i] = l1s_encode_rxlev(IL_for_rxlev);
3848 }
3849 }
3850
3851 // If the Read phase is done during fn_mod26 = 13 --> measurements have been done
3852 // during a PTCCH frame
3853 if (l1s.actual_time.t2 == 13)
3854 {
3855 ((T_L1P_ITMEAS_IND *)(msg->SigP))->position = PTCCH_FRAME;
3856 }
3857 else // Measurements done during a search frame
3858 {
3859 ((T_L1P_ITMEAS_IND *)(msg->SigP))->position = SEARCH_FRAME;
3860 }
3861
3862 // send message...
3863 os_send_sig(msg, L1C1_QUEUE);
3864 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
3865
3866 // ITMEAS is a 'one shot' task --> disable task
3867 l1a_l1s_com.l1s_en_task[ITMEAS] = TASK_DISABLED;
3868 } // End if "task enabled and semaphore false"
3869
3870 // End of task -> task must become INACTIVE.
3871 l1s.task_status[ITMEAS].current_status = INACTIVE;
3872
3873 // Switch DSP read page if needed
3874 if(l1pa_l1ps_com.itmeas.dsp_r_page_switch_req)
3875 {
3876 // Set flag used to change the read page at the end of "l1_synch".
3877 l1s_dsp_com.dsp_r_page_used = TRUE;
3878 }
3879 }
3880
3881 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
3882 #endif // MOVE_IN_INTERNAL_RAM
3883
3884 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
3885 #endif
3886 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END