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comparison src/cs/layer1/tpu_drivers/source/tpudrv.c @ 0:b6a5e36de839

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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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-1:000000000000 0:b6a5e36de839
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename tpudrv.c
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8 /*
9 * TPUDRV.C
10 *
11 * TPU driver for Pole Star
12 *
13 *
14 * Copyright (c) Texas Instruments 1996
15 *
16 */
17
18 #include "l1_macro.h"
19 #include "iq.h"
20 #include "l1_confg.h"
21 #include "l1_const.h"
22 #include "l1_types.h"
23
24 #if (AUDIO_TASK == 1)
25 #include "l1audio_const.h"
26 #include "l1audio_cust.h"
27 #include "l1audio_defty.h"
28 #endif
29
30 #if (L1_GTT == 1)
31 #include "l1gtt_const.h"
32 #include "l1gtt_defty.h"
33 #endif
34
35 #if (L1_MIDI == 1)
36 #include "l1midi_defty.h"
37 #endif
38
39 #include "sys_types.h"
40
41 #if TESTMODE
42 #include "l1tm_defty.h"
43 #endif
44
45 #if (L1_MP3 == 1)
46 #include "l1mp3_defty.h"
47 #endif
48
49 #if (L1_MIDI == 1)
50 #include "l1midi_defty.h"
51 #endif
52
53 #if (L1_AAC == 1)
54 #include "l1aac_defty.h"
55 #endif
56 #include "l1_defty.h"
57 #include "tpudrv.h"
58 #include "sys_types.h"
59 #include "clkm.h"
60 #include "l1_time.h"
61 #include "l1_varex.h"
62 #include "l1_trace.h"
63
64 #if (L1_MADC_ON == 1)
65 #if (RF_FAM == 61)
66 #include "drp_api.h"
67 #include "l1_rf61.h"
68 #include "drp_drive.h"
69 #include "tpudrv61.h"
70 extern T_DRP_REGS_STR *drp_regs;
71 #endif
72 #endif //L1_MADC_ON
73
74 /* RFTime environment */
75 #if defined (HOST_TEST)
76 #include "hostmacros.h"
77 #endif
78
79
80 /*
81 * VEGA and OMEGA receive windows - Defined in Customer-specific file
82 */
83
84 extern UWORD32 debug_tpu;
85
86 #if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 )
87 // WCS Patch : ADC during RX or TX
88 extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc);
89 #endif
90
91 /*
92 * Global Variables
93 */
94 // GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx
95 //------------------------------------------------------------
96 SYS_UWORD16 *TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
97
98
99 /*--------------------------------------------------------------*/
100 /* TPU_Reset : Reset the TPU */
101 /*--------------------------------------------------------------*/
102 /* Parameters : on/off(1/0) */
103 /* Return : none */
104 /* Functionality : ) Reset the TPU */
105 /*--------------------------------------------------------------*/
106 void TPU_Reset(SYS_UWORD16 on)
107 {
108 if (on)
109 {
110 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_RESET;
111 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
112 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
113 }
114 else
115 {
116 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET;
117 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
118 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
119 }
120 }
121
122 /*--------------------------------------------------------------*/
123 /* TSP_Reset : Reset the TSP */
124 /*--------------------------------------------------------------*/
125 /* Parameters : on/off(1/0) */
126 /* Return : none */
127 /* Functionality : ) Reset the TSP */
128 /*--------------------------------------------------------------*/
129 void TSP_Reset(SYS_UWORD16 on)
130 {
131 if (on)
132 {
133 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TSP_CTRL_RESET;
134 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
135 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
136 }
137 else
138 {
139 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET;
140 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
141 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
142 }
143 }
144
145 /*--------------------------------------------------------------*/
146 /* TPU_SPIReset : Reset the SPI of the TPU */
147 /*--------------------------------------------------------------*/
148 /* Parameters : on/off(1/0) */
149 /* Return : none */
150 /* Functionality : ) the SPI of the TPU */
151 /*--------------------------------------------------------------*/
152
153 void TPU_SPIReset(SYS_UWORD16 on)
154 {
155 if (on)
156 {
157 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_SPI_RST;
158 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
159 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
160 }
161 else
162 {
163 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST;
164 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
165 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
166 }
167 }
168
169 /*--------------------------------------------------------------*/
170 /* TPU_ClkEnable : */
171 /*--------------------------------------------------------------*/
172 /* Parameters : on/off(1/0) */
173 /* Return : none */
174 /* Functionality : Enable the TPU clock */
175 /*--------------------------------------------------------------*/
176
177 void TPU_ClkEnable(SYS_UWORD16 on)
178 {
179 if (on)
180 {
181 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_CLK_EN;
182 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
183 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
184 }
185 else
186 {
187 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN;
188 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
189 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
190 }
191 }
192
193 /*--------------------------------------------------------------*/
194 /* TPU_Frame_ItOn : */
195 /*--------------------------------------------------------------*/
196 /* Parameters : bit of it to enable */
197 /* Return : none */
198 /* Functionality : Enable frame it */
199 /*--------------------------------------------------------------*/
200
201 /*-----------------------------------------------------------*/
202 /* Warning read modify write access to TPU_INT_CTRL register */
203 /* may generate problems using Hyperion. */
204 /*-----------------------------------------------------------*/
205
206 void TPU_FrameItOn(SYS_UWORD16 it)
207 {
208 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it;
209 }
210
211 void TPU_FrameItEnable(void)
212 {
213 #if W_A_ITFORCE
214 (*(volatile SYS_UWORD16 *)TPU_INT_CTRL) |= TPU_INT_ITD_F;
215 #else
216 // enable IT_DSP generation on next frame
217 // reset by DSP when IT occurs
218 (*(volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_D_ENBL;
219 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
220 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL));
221 #endif
222 }
223
224 /*--------------------------------------------------------------*/
225 /* TPU_check_IT_DSP : */
226 /*--------------------------------------------------------------*/
227 /* Parameters : none */
228 /* Return : none */
229 /* Functionality : check if an IT DSP still pending */
230 /*--------------------------------------------------------------*/
231 BOOL TPU_check_IT_DSP(void)
232 { // return TRUE if an IT DSP still pending.
233 return( (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL));
234 }
235
236 /*--------------------------------------------------------------*/
237 /* TPU_DisableAllIt : */
238 /*--------------------------------------------------------------*/
239 /* Parameters : none */
240 /* Return : none */
241 /* Functionality : Disabl all it */
242 /*--------------------------------------------------------------*/
243 void TPU_DisableAllIt()
244 {
245 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) |= TPU_INT_ITF_M | TPU_INT_ITP_M | TPU_INT_ITD_M;
246
247 }
248
249
250 /*
251 * TP_Program
252 *
253 * Write a null-terminated scenario into TPU memory at a given start address
254 * (Do not write terminating 0)
255 *
256 */
257 void TP_Program(const SYS_UWORD16 *src)
258 {
259 /* Write TPU instructions until SLEEP */
260 while (*src)
261 {
262 *TP_Ptr++ = *src++;
263 }
264 }
265
266
267 void TP_Reset(SYS_UWORD16 on)
268 {
269 if (on) {
270 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= (TPU_CTRL_RESET | TSP_CTRL_RESET);
271 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
272 }
273 else {
274 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET | TSP_CTRL_RESET);
275 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
276 }
277 }
278
279 void TP_Enable(SYS_UWORD16 on)
280 {
281 if(on)
282 {
283 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_T_ENBL;
284
285 // Some time shall be wait before leaving the function to ensure that bit has been taken
286 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
287 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
288 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
289 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
290 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
291 }
292 else
293 {
294 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL;
295 // Some time shall be wait before leaving the function to ensure that bit has been taken
296 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
297 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
298 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
299 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
300 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
301 }
302 }
303
304
305 #if 0 /* FreeCalypso: function not present in TCS211 */
306 /*-----------------------------------------------------------------------*/
307 /* Function name: TPU_wait_idle */
308 /*-----------------------------------------------------------------------*/
309 /* */
310 /* Parameters: None */
311 /* */
312 /* Return: None */
313 /* */
314 /*-----------------------------------------------------------------------*/
315 /* Description: Wait until TPU scenario execution is complete */
316 /* */
317 /*-----------------------------------------------------------------------*/
318 void TPU_wait_idle(void)
319 {
320 while( ((*(volatile SYS_UWORD16 *) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE)
321 {
322 wait_ARM_cycles(convert_nanosec_to_cycles(3000));
323 }
324 }
325 #endif
326
327
328 /*
329 * l1dmacro_idle
330 *
331 * Write SLEEP instruction, start TPU and reset pointer
332 */
333 void l1dmacro_idle (void)
334 {
335 *TP_Ptr++ = TPU_SLEEP;
336
337 /* start TPU */
338 TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
339 TP_Enable(1);
340 }
341
342 /*
343 * l1dmacro_offset
344 *
345 * Set OFFSET register
346 *
347 */
348 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time)
349 {
350 // WARNING: 'relative time' and 'offset_value' must always be comprised
351 // between 0 and TPU_CLOCK_RANGE !!!
352
353 if (relative_time != IMM) // IMM indicates to set directly without AT
354 {
355 *TP_Ptr++ = TPU_FAT(relative_time);
356 }
357 *TP_Ptr++ = TPU_OFFSET(offset_value);
358 }
359
360 /*
361 * l1dmacro_synchro
362 *
363 * Set synchro register
364 */
365 void l1dmacro_synchro (UWORD32 when, UWORD32 value)
366 {
367 // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!!
368 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
369 trace_fct(CST_L1DMACRO_SYNCHRO, -1);
370 #endif
371
372 if (value != IMM) // IMM indicates to set directly without AT
373 {
374 *TP_Ptr++ = TPU_FAT(when);
375 }
376
377 *TP_Ptr++ = TPU_SYNC(value);
378 l1s.tpu_offset_hw = value; // memorize the offset set into the TPU.
379 }
380
381
382 /*
383 * l1dmacro_adc_read
384 *
385 */
386 void l1dmacro_adc_read_rx(void)
387 {
388
389 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
390 // TSP needs to be configured in order to send serially to Omega
391
392 // *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration
393 *TP_Ptr++ = TPU_WAIT (5);
394 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
395 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send
396 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
397 *TP_Ptr++ = TPU_WAIT (5);
398 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00);
399 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
400
401 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
402 #if (GSM_IDLE_RAM == 0)
403 l1_trace_ADC(0);
404 #else
405 l1_trace_ADC_intram(0);
406 #endif
407 #endif
408 #endif
409
410 #if (L1_MADC_ON == 1)
411 #if (ANLG_FAM == 11)
412
413 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
414 #if (GSM_IDLE_RAM == 0)
415 l1_trace_ADC(0);
416 #else
417 l1_trace_ADC_intram(0);
418 #endif
419 #endif
420 #endif
421
422 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
423 // WCS patch: ADC during RX
424 GC_SetAdcInfo(0);
425 #endif
426 #endif
427 }
428
429
430 #if (CODE_VERSION != SIMULATION)
431 #if (L1_MADC_ON ==1)
432 /*
433 * l1dmacro_adc_read_rx_cs_mode0
434 *
435 * Purpose:
436 * ======
437 * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0
438 * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ
439 * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ
440 * increases and can be as high as 360 seconds (Maximum Value)
441 * This can result in battery related issues like phone powering off without MMI indication.
442 */
443
444
445 void l1dmacro_adc_read_rx_cs_mode0(void)
446 {
447 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC);
448 *TP_Ptr++ = TPU_WAIT (2);
449 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0);
450
451 #if (L1_MADC_ON == 1)
452 #if (ANLG_FAM == 11)
453
454 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
455 #if (GSM_IDLE_RAM == 0)
456 l1_trace_ADC(0);
457 #else
458 l1_trace_ADC_intram(0);
459 #endif
460 #endif
461 #endif
462
463 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
464 // WCS patch: ADC during RX
465 GC_SetAdcInfo(0);
466 #endif
467 #endif
468 }
469
470
471 #endif //If MADC is enabled
472 #endif //If Not Simulation
473
474 /*
475 * l1dmacro_adc_read_tx
476 *
477 */
478
479
480 #if (ANLG_FAM != 11)
481 void l1dmacro_adc_read_tx(UWORD32 when)
482 #else
483 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
484 #endif
485 {
486
487 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
488
489 *TP_Ptr++ = TPU_FAT (when);
490 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
491 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC|BULON|BULENA); // Load data to send
492 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
493 *TP_Ptr++ = TPU_WAIT (5);
494 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON|BULENA);
495 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
496
497 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
498 l1_trace_ADC(1);
499 #endif
500 #endif
501
502 #if (L1_MADC_ON == 1)
503 #if (ANLG_FAM == 11)
504 *TP_Ptr++ = TPU_FAT (when);
505 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
506 *TP_Ptr++ = TPU_WAIT (2);
507 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
508
509 #if 1 // TEMP MEASUREMENT - uncomment and test after MADC
510 #if (RF_FAM == 61)
511 *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \
512 *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \
513 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \
514 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \
515 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \
516 //TEMP_MEAS: Call TEMP Conv Script in DRP
517 //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL));
518 #endif
519
520 #endif
521
522 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
523 l1_trace_ADC(1);
524 #endif
525
526 #endif
527 #endif //L1_MADC_ON
528
529 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
530 // WCS patch: ADC during TX
531 GC_SetAdcInfo(1);
532 #endif
533
534
535 }
536
537
538 /*
539 #if (RF_FAM == 61)
540
541 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
542 {
543 int i;
544
545 *TP_Ptr++ = TPU_FAT (when);
546 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
547 *TP_Ptr++ = TPU_WAIT (2);
548 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
549
550 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
551 l1_trace_ADC(1);
552 #endif
553
554
555 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
556 // WCS patch: ADC during TX
557 GC_SetAdcInfo(1);
558 #endif
559 }
560
561 #endif
562 */
563
564 /*
565 * l1dmacro_set_frame_it
566 *
567 */
568 void l1dmacro_set_frame_it(void)
569 {
570 TPU_FrameItEnable();
571 }