# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1593390433 0
# Node ID ba3693cbd40e2c3e1ed8529338ffe7bf426a7633
# Parent  ae3106eb5923f3af9c904908beb821e8217a4b08
src/cs: sync with Magnetite

diff -r ae3106eb5923 -r ba3693cbd40e src/cs/drivers/drv_app/uart/uartfax.c
--- a/src/cs/drivers/drv_app/uart/uartfax.c	Sun Jun 28 23:54:05 2020 +0000
+++ b/src/cs/drivers/drv_app/uart/uartfax.c	Mon Jun 29 00:27:13 2020 +0000
@@ -118,6 +118,10 @@
   #include "armio/armio.h"
 #endif
 
+#ifdef CONFIG_TANGO_MODEM
+extern SYS_UWORD8 AI_Tango_pinmux[4];
+#endif
+
 /* 
  * Maximal value for an unsigned 32 bits.
  */
@@ -2596,6 +2600,9 @@
             uart->tx_stopped_by_driver = 0;
             #ifdef CONFIG_TARGET_GTAMODEM
                 AI_ResetBit(1);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[0] == 0x82)
+                    AI_ResetBit(1);
             #endif
 
 #if ((CHIPSET != 5) && (CHIPSET != 6))
@@ -3021,9 +3028,15 @@
      * DCD should start HIGH (not asserted).
      */
 
+#ifdef CONFIG_TANGO_MODEM
+  if (AI_Tango_pinmux[1] & 0x08) {
+#endif
     *((volatile SYS_UWORD16 *) EXTENDED_MCU_REG) &= ~(1 << IO_DCD);
     AI_ConfigBitAsOutput (ARMIO_DCD);
     AI_SetBit (ARMIO_DCD);
+#ifdef CONFIG_TANGO_MODEM
+  }
+#endif
 
     /*
      * Select I/O for DTR and configure it as input.
@@ -3031,6 +3044,9 @@
      * or rising edge is selected according to the state of DTR.
      */
     
+#ifdef CONFIG_TANGO_MODEM
+  if (AI_Tango_pinmux[1] & 0x80) {
+#endif
     *((volatile SYS_UWORD16 *) ASIC_CONFIG_REG) &= ~(1 << IO_DTR);
     AI_ConfigBitAsInput (ARMIO_DTR);
     uart->dtr_level = AI_ReadBit (ARMIO_DTR);
@@ -3041,6 +3057,10 @@
         AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
         
     AI_UnmaskIT (ARMIO_MASKIT_GPIO);
+#ifdef CONFIG_TANGO_MODEM
+  } else
+    uart->dtr_level = 0;
+#endif
 
     /*
      * Reset the 2 indexes of the circular buffer of 2 elements.
@@ -3223,7 +3243,10 @@
 
     WRITE_UART_REGISTER (uart, IER, 0x00);
 
-#if UARTFAX_CLASSIC_DTR_DCD
+#ifdef CONFIG_TANGO_MODEM
+    if (AI_Tango_pinmux[1] & 0x80)
+      AI_MaskIT (ARMIO_MASKIT_GPIO);
+#elif UARTFAX_CLASSIC_DTR_DCD
     AI_MaskIT (ARMIO_MASKIT_GPIO);
 #elif (CHIPSET == 12)
     DISABLE_DSR_INTERRUPT (uart);
@@ -3369,6 +3392,9 @@
      * Read the state of DTR and select the edge.
      */
          
+#ifdef CONFIG_TANGO_MODEM
+  if (AI_Tango_pinmux[1] & 0x80) {
+#endif
     uart->dtr_level = AI_ReadBit (ARMIO_DTR);
     
     if (uart->dtr_level)
@@ -3377,6 +3403,11 @@
         AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
         
     AI_UnmaskIT (ARMIO_MASKIT_GPIO);
+#ifdef CONFIG_TANGO_MODEM
+  } else
+    uart->dtr_level = 0;
+#endif
+
 #elif (CHIPSET == 12)
     /*
      * Read the state of DTR - No need to reload MSR register since its value
@@ -3595,25 +3626,49 @@
             uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
             */
 #endif
-        
+
+        /*
+         * Openmoko made the change of enabling hardware assisted CTS
+         * flow control in the UART when RTS/CTS flow control is used -
+         * it is a change which we have retained in FreeCalypso -
+         * but they forgot to turn this hw mode off if RTS/CTS flow control
+         * is deselected at the application level.  We (FreeCalypso)
+         * are now fixing the latter defect ourselves.
+         */
         if (fcMode == fc_rts) {
-#if 1 // Dmitriy: enable hardware assisted CTS 
-            volatile SYS_UWORD8 oldValue;
+            /* begin Openmoko change */
+            SYS_UWORD8 oldValue;
 
             oldValue = READ_UART_REGISTER (uart, LCR);
-            
+
             // LCR value to allow acces to EFR
-     
+
             WRITE_UART_REGISTER (uart, LCR, 0xBF);
-            
+
             // enable hardware assisted CTS
-            
+
             SET_BIT (uart, EFR, AUTO_CTS_BIT);
-            
-            WRITE_UART_REGISTER (uart, LCR, oldValue);    
-#endif
+
+            WRITE_UART_REGISTER (uart, LCR, oldValue);
+            /* end Openmoko change */
+
             if (uart->rts_level)
                 uart->tx_stopped_by_driver = 1;
+        } else {
+            /* FreeCalypso addition: turn off OM-added Auto-CTS */
+            SYS_UWORD8 oldValue;
+
+            oldValue = READ_UART_REGISTER (uart, LCR);
+
+            // LCR value to allow acces to EFR
+
+            WRITE_UART_REGISTER (uart, LCR, 0xBF);
+
+            // disable hardware assisted CTS
+
+            RESET_BIT (uart, EFR, AUTO_CTS_BIT);
+
+            WRITE_UART_REGISTER (uart, LCR, oldValue);
         }
 
         /*
@@ -4329,6 +4384,9 @@
 	#ifdef CONFIG_TARGET_GTAMODEM
 	    if (uart->tx_stopped_by_driver)
 		AI_SetBit(1);
+	#elif defined(CONFIG_TANGO_MODEM)
+	    if (AI_Tango_pinmux[0] == 0x82 && uart->tx_stopped_by_driver)
+		AI_SetBit(1);
 	#endif
 
         /*
@@ -4755,6 +4813,9 @@
             /* Turn on DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_ResetBit (ARMIO_DCD);
             #else
                 AI_ResetBit (ARMIO_DCD);
             #endif
@@ -4762,6 +4823,9 @@
             /* Turn off DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_SetBit (ARMIO_DCD);
             #else
                 AI_SetBit (ARMIO_DCD);
             #endif
@@ -4791,6 +4855,9 @@
             /* Turn on DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_ResetBit (ARMIO_DCD);
             #else
                 AI_ResetBit (ARMIO_DCD);
             #endif
@@ -4798,6 +4865,9 @@
             /* Turn off DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_SetBit (ARMIO_DCD);
             #else
                 AI_SetBit (ARMIO_DCD);
             #endif
diff -r ae3106eb5923 -r ba3693cbd40e src/cs/drivers/drv_core/armio/armio.c
--- a/src/cs/drivers/drv_core/armio/armio.c	Sun Jun 28 23:54:05 2020 +0000
+++ b/src/cs/drivers/drv_core/armio/armio.c	Mon Jun 29 00:27:13 2020 +0000
@@ -35,6 +35,12 @@
 #include "armio/armio.h"
 #include "abb/abb.h"	 // for AI_Power function : to be removed, use ABB_Power_Off in abb.c file instead !!!
 
+#ifdef CONFIG_TANGO_MODEM
+#include "ffs/ffs_api.h"
+
+SYS_UWORD8 AI_Tango_pinmux[4];
+#endif
+
 #if (CHIPSET != 12)
 /*
  * AI_EnableBit
@@ -267,33 +273,33 @@
     // For targets other than GTM900, we enable the audio amplifier
     // if we are in an MMI!=0 build - for ACI builds use the AT@SPKR command.
 #ifdef CONFIG_TARGET_GTM900
-      *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F01;
+      *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F05;
 #elif (MMI != 0) || defined(CONFIG_GPIO1_HIGH)
-      *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F02;
+      *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F06;
 #else
-      *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F00;
+      *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F04;
 #endif
 
     // ARMIO_CNTL_REG register configuration :
     // set IOs 1,2,5,7,9,14 and 15 as ouputs.
-    // bits conditionalized on CONFIG_TARGET_GTAMODEM or CONFIG_TARGET_FCFAM
-    // are FreeCalypso additions
-    #if defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_FCFAM) || \
-        defined(CONFIG_TARGET_GTM900)
+    // all others are FreeCalypso additions
+    #if defined(CONFIG_GPIO046_OUTPUTS) || defined(CONFIG_TARGET_GTM900)
       AI_ConfigBitAsOutput(0);
     #endif
-    AI_ConfigBitAsOutput(1);
-    #ifndef CONFIG_TARGET_LEONARDO	/* GPIO 2 is an input on Leonardo! */
-      AI_ConfigBitAsOutput(2);
+    #ifndef CONFIG_TANGO_MODEM	/* we do dynamic config on Tango instead */
+      AI_ConfigBitAsOutput(1);
+      #ifndef CONFIG_TARGET_LEONARDO	/* GPIO 2 is an input on Leonardo! */
+        AI_ConfigBitAsOutput(2);
+      #endif
+      #ifdef CONFIG_GPIO3_OUTPUT
+        AI_ConfigBitAsOutput(3);
+      #endif
     #endif
-    #ifdef CONFIG_GPIO3_OUTPUT
-      AI_ConfigBitAsOutput(3);
-    #endif
-    #if defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_FCFAM)
+    #ifdef CONFIG_GPIO046_OUTPUTS
       AI_ConfigBitAsOutput(4);
     #endif
     AI_ConfigBitAsOutput(5);
-    #if defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_FCFAM)
+    #ifdef CONFIG_GPIO046_OUTPUTS
       AI_ConfigBitAsOutput(6);
     #endif
     AI_ConfigBitAsOutput(7);
@@ -314,6 +320,83 @@
   #endif
 }
 
+#ifdef CONFIG_TANGO_MODEM
+void AI_Init_Tango_pinmux(void)
+{
+	ffs_file_read("/etc/tango-pinmux", AI_Tango_pinmux, 4);
+	/* apply this config */
+	if (AI_Tango_pinmux[0] & 0x80) {
+		if (AI_Tango_pinmux[0] & 1)
+			AI_SetBit(1);
+		else
+			AI_ResetBit(1);
+		AI_ConfigBitAsOutput(1);
+	}
+	/* GPIO2 config */
+	if (AI_Tango_pinmux[1] & 0x02) {
+		if (AI_Tango_pinmux[1] & 0x01)
+			AI_SetBit(2);
+		else
+			AI_ResetBit(2);
+		AI_ConfigBitAsOutput(2);
+	}
+	/* GPIO3 config */
+	if (AI_Tango_pinmux[1] & 0x20) {
+		if (AI_Tango_pinmux[1] & 0x10)
+			AI_SetBit(3);
+		else
+			AI_ResetBit(3);
+		AI_ConfigBitAsOutput(3);
+	}
+	/* RESET_OUT/IO7 config */
+	if (AI_Tango_pinmux[2] & 0x08) {
+		AI_EnableBit(3);
+		if (AI_Tango_pinmux[2] & 0x02) {
+			if (AI_Tango_pinmux[2] & 0x01)
+				AI_SetBit(7);
+			else
+				AI_ResetBit(7);
+		} else
+			AI_ConfigBitAsInput(7);
+	}
+	/* MCSI/GPIO config */
+	if (AI_Tango_pinmux[2] & 0x80) {
+		if (AI_Tango_pinmux[3] & 0x10) {
+			if (AI_Tango_pinmux[3] & 0x01)
+				AI_SetBit(9);
+			else
+				AI_ResetBit(9);
+		} else
+			AI_ConfigBitAsInput(9);
+		AI_EnableBit(5);
+		AI_EnableBit(6);
+		AI_EnableBit(7);
+		AI_EnableBit(8);
+		if (AI_Tango_pinmux[3] & 0x20) {
+			if (AI_Tango_pinmux[3] & 0x02)
+				AI_SetBit(10);
+			else
+				AI_ResetBit(10);
+			AI_ConfigBitAsOutput(10);
+		}
+		if (AI_Tango_pinmux[3] & 0x40) {
+			if (AI_Tango_pinmux[3] & 0x04)
+				AI_SetBit(11);
+			else
+				AI_ResetBit(11);
+			AI_ConfigBitAsOutput(11);
+		}
+		if (AI_Tango_pinmux[3] & 0x80) {
+			if (AI_Tango_pinmux[3] & 0x08)
+				AI_SetBit(12);
+			else
+				AI_ResetBit(12);
+			AI_ConfigBitAsOutput(12);
+		}
+	}
+}
+#endif
+
 /*
  * AI_SelectIOForIT
  *
diff -r ae3106eb5923 -r ba3693cbd40e src/cs/system/main/init.c
--- a/src/cs/system/main/init.c	Sun Jun 28 23:54:05 2020 +0000
+++ b/src/cs/system/main/init.c	Mon Jun 29 00:27:13 2020 +0000
@@ -354,7 +354,8 @@
         #else
           #if (BOARD==35)
             *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
-          #elif defined(CONFIG_TARGET_PIRELLI) || defined(CONFIG_TARGET_DSAMPLE)
+          #elif defined(CONFIG_TARGET_PIRELLI) || \
+                defined(CONFIG_TARGET_DSAMPLE) || defined(CONFIG_TARGET_TANGO)
             /*
              * Pirelli's version of this Init_Target() function
              * in their fw sets the ASIC_CONF register to 0x6050,
@@ -365,6 +366,10 @@
              * PWL and LPG pin configs on the D-Sample: the DS board
              * has LEDs for PWL and for LPG and they work as expected,
              * thus the board is clearly wired for this pin config.
+             *
+             * Finally, we set the same config on Tango targets:
+             * DSR_MODEM/LPG is configured as LPG in order to avoid
+             * the floating input, whereas LT/PWL works better as PWL.
              */
             *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050;
           #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_GTM900)
@@ -888,6 +893,10 @@
 	bspUicc_bootInit();
     #endif
   #endif
+
+  #ifdef CONFIG_TANGO_MODEM
+    AI_Init_Tango_pinmux();
+  #endif
 }
 
 /*