FreeCalypso > hg > fc-selenite
changeset 83:92fde62400ef
.../gcc/exceptions.S: added 2nd part that was missing in Citrine
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 20 Jul 2018 18:21:46 +0000 |
parents | 6afaa5cb7392 |
children | 32bcc299ef55 |
files | src/cs/system/main/gcc/exceptions.S |
diffstat | 1 files changed, 46 insertions(+), 7 deletions(-) [+] |
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--- a/src/cs/system/main/gcc/exceptions.S Fri Jul 20 17:33:14 2018 +0000 +++ b/src/cs/system/main/gcc/exceptions.S Fri Jul 20 18:21:46 2018 +0000 @@ -1,14 +1,8 @@ /* * This module contains ARM exception handlers which used to be - * in chipsetsw/system/Main/int.s in TI's Leonardo code. + * in chipsetsw/system/Main/int.s in TI's original version. */ - .section "except_stack","aw",%nobits - .balign 4 - .space 512 - .globl _Except_Stack_SP -_Except_Stack_SP: - .text .code 32 @@ -84,3 +78,48 @@ mov r0,r11 @ put index into 1st argument b dar_exception + +@ the second part + +/* + * For the SP-in-RAM validity check, we use the following simplification: + * it doesn't really matter what the actual IRAM and XRAM sizes are on + * any given target, as the address decoder hooked up to the ARM7TDMI core + * always decodes the full 8 MiB address range for each, causing the + * actual memories to be aliased multiple times in those two ranges. + * Furthermore, the XRAM address range falls right after the IRAM one, + * thus we can get away with only a single range check. + */ + +#define RAM_LOW 0x00800000 +#define RAM_HIGH 0x01800000 + +#define XDUMP_STACK_SIZE 20 + + .globl exception +exception: + ldr r12,=xdump_buffer + ldr r11,[r12,#4*13] @ get svc mode r13 + add r12,r12,#4*18 @ base of stack buffer + + @ check if svc r13(sp) is within internal/external RAM. + @ It *could* be invalid. + cmp r11,#RAM_LOW + blt nostack + mov r0,#RAM_HIGH + sub r0,r0,#XDUMP_STACK_SIZE + cmp r11,r0 + bge nostack + +stack_range: + ldmfd r11!,{r0-r9} @ copy ten stack words.. + stmia r12!,{r0-r9} + ldmfd r11!,{r0-r9} @ copy ten stack words.. + stmia r12!,{r0-r9} + +nostack: + @ we're finished saving all state. + @ Now execute C code for more flexibility. + @ set up a stack for this C call + ldr sp,=_Stack_segment_end + b dar_reset