FreeCalypso > hg > fc-selenite
changeset 168:aa2956979fcb
src/cs/system: MEMIF and init updates from Magnetite
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Wed, 19 Jun 2019 04:05:38 +0000 |
| parents | 5b0e7f9b3d05 |
| children | 9d46c005da91 |
| files | src/cs/system/bootloader/src/bootloader.s src/cs/system/main/init.asm src/cs/system/main/init.c |
| diffstat | 3 files changed, 75 insertions(+), 27 deletions(-) [+] |
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--- a/src/cs/system/bootloader/src/bootloader.s Wed Jun 19 03:57:35 2019 +0000 +++ b/src/cs/system/bootloader/src/bootloader.s Wed Jun 19 04:05:38 2019 +0000 @@ -161,9 +161,19 @@ .endif .elseif BOARD = 41 ; D-Sample FLASH CS0 + +; FreeCalypso change, please see MEMIF-wait-states document +; in the freecalypso-docs repository for the explanation. + + .if VCXO_26MHZ = 1 +CS0_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable +CS1_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable +CS2_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable + .else CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable + .endif CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable @@ -252,7 +262,7 @@ CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register ; Use DPLL, Divide by 1 -DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state +DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled @@ -264,7 +274,7 @@ CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register ; Use DPLL, Divide by 1 -DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state +DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled @@ -276,7 +286,7 @@ CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register ; Use DPLL, Divide by 1 -DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state +DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled @@ -672,4 +682,4 @@ .word end .end - \ No newline at end of file +
--- a/src/cs/system/main/init.asm Wed Jun 19 03:57:35 2019 +0000 +++ b/src/cs/system/main/init.asm Wed Jun 19 04:05:38 2019 +0000 @@ -170,9 +170,19 @@ .elseif BOARD = 41 +; FreeCalypso change, please see MEMIF-wait-states document +; in the freecalypso-docs repository for the explanation. + + .if VCXO_26MHZ = 1 +CS0_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable +CS1_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable +CS2_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable + .else CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable + .endif + CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0xe85 ; default reset value
--- a/src/cs/system/main/init.c Wed Jun 19 03:57:35 2019 +0000 +++ b/src/cs/system/main/init.c Wed Jun 19 04:05:38 2019 +0000 @@ -362,12 +362,14 @@ * DSR_MODEM pin. */ *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050; - #elif defined(CONFIG_TARGET_GTAMODEM) + #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_GTM900) /* * The DSR_MODEM/LPG Calypso signal is unconnected on * Openmoko's modem, so let's mux it as LPG (output) * so it doesn't float, like Foxconn seem to have done * on the Pirelli. + * + * On the GTM900 module this signal is explicitly defined as LPG. */ *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6040; #else @@ -500,15 +502,16 @@ DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); #if (CHIPSET == 8) DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6); - #elif (CHIPSET == 10) + #elif (CHIPSET == 10) || (CHIPSET == 11) DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); #else #error "We only have DPLL setup for CHIPSETs 8 and 10" #endif CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ /* - * FreeCalypso change: memory timings and widths - * are target-dependent. + * FreeCalypso change: memory timings and widths are target-dependent; + * please refer to the MEMIF-wait-states document in the freecalypso-docs + * repository for the full explanation. */ #ifdef CONFIG_TARGET_PIRELLI /* @@ -520,30 +523,18 @@ MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); - #elif defined(CONFIG_TARGET_FCFAM) + #elif defined(CONFIG_TARGET_C155) /* - * The settings currently adopted for the FreeCalypso - * hardware family, only nCS0, nCS1 and nCS2 are used - * presently. + * C155/156 official fw MEMIF config is almost the same as Pirelli's, + * only nCS4 WS is different, but nCS4 is unused on this model... */ MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); - MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); - MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0); - #elif defined(CONFIG_TARGET_DSAMPLE) && (CHIPSET == 8) - /* - * On D-Sample C05 (older Calypso silicon version) the clocks - * run slower: the ARM clock runs at 39 MHz instead of 52 MHz. - * Therefore, we need to use fewer wait states to effect - * the same memory speed. - */ - MEM_INIT_CS0(2, MEM_DVS_16, MEM_WRITE_EN, 0); - MEM_INIT_CS1(2, MEM_DVS_16, MEM_WRITE_EN, 0); - MEM_INIT_CS2(2, MEM_DVS_16, MEM_WRITE_EN, 0); - MEM_INIT_CS3(2, MEM_DVS_16, MEM_WRITE_EN, 0); - MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); - #else + MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0); + #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \ + defined(CONFIG_TARGET_GTAMODEM) /* * The original settings from Openmoko, * only nCS0 and nCS1 are actually used, @@ -555,6 +546,43 @@ MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); + #elif defined(CONFIG_TARGET_J100) + /* + * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS: + * it appears that SE J100 has its ringtone melody generator chip + * hooked up there. + */ + MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); + #elif (CHIPSET == 8) + /* + * Our only Calypso C05 target is Mother Mychaela's D-Sample board. + * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns, + * so we should be good on this board. + */ + MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); + #elif (CHIPSET == 10) || (CHIPSET == 11) + /* + * Default for Calypso C035 targets in the absence of a more specific + * selection above. We put the WS=4 memory-oriented setting on all + * chip selects so we automatically cover targets with a second flash + * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even + * weirder targets with XRAM somewhere other than nCS1. + */ + MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0); + #else + #error "Unknown MEMIF configuration" #endif MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0); MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);