| Sat, 21 Jul 2018 00:32:56 +0000 |
Mychaela Falconia |
configure-gcc.sh: created
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| Sat, 21 Jul 2018 00:22:35 +0000 |
Mychaela Falconia |
components/main_ir: ramvecs module now goes outside of libs
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| Sat, 21 Jul 2018 00:21:50 +0000 |
Mychaela Falconia |
gcc/makefile-body: created
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| Fri, 20 Jul 2018 23:39:27 +0000 |
Mychaela Falconia |
.../main/gcc/bootentry.S: the literal pool needs to be arranged
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| Fri, 20 Jul 2018 23:14:00 +0000 |
Mychaela Falconia |
src/cs/system/main/gcc/bootentry.S: written
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| Fri, 20 Jul 2018 20:53:45 +0000 |
Mychaela Falconia |
scripts/test-setup-tms470.sh: updated
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| Fri, 20 Jul 2018 20:44:02 +0000 |
Mychaela Falconia |
components/libsys_{fl,ir}: created
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| Fri, 20 Jul 2018 20:36:19 +0000 |
Mychaela Falconia |
src/libsys: pieced together from Citrine
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| Fri, 20 Jul 2018 20:22:38 +0000 |
Mychaela Falconia |
components/main_ir: created for assembly modules
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| Fri, 20 Jul 2018 19:36:25 +0000 |
Mychaela Falconia |
gcc/ld-script.src: additional polish
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| Fri, 20 Jul 2018 18:21:46 +0000 |
Mychaela Falconia |
.../gcc/exceptions.S: added 2nd part that was missing in Citrine
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| Fri, 20 Jul 2018 17:33:14 +0000 |
Mychaela Falconia |
linker script for gcc fw build: initial version put together
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| Fri, 20 Jul 2018 09:38:01 +0000 |
Mychaela Falconia |
targets/*.m4 created for linker script generation in gcc version
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| Fri, 20 Jul 2018 07:36:23 +0000 |
Mychaela Falconia |
created int_dummy.S with INT_*() functions for tcc.c
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