log

age author description
2018-07-21 Mychaela Falconia configure-gcc.sh: created
2018-07-21 Mychaela Falconia components/main_ir: ramvecs module now goes outside of libs
2018-07-21 Mychaela Falconia gcc/makefile-body: created
2018-07-20 Mychaela Falconia .../main/gcc/bootentry.S: the literal pool needs to be arranged
2018-07-20 Mychaela Falconia src/cs/system/main/gcc/bootentry.S: written
2018-07-20 Mychaela Falconia scripts/test-setup-tms470.sh: updated
2018-07-20 Mychaela Falconia components/libsys_{fl,ir}: created
2018-07-20 Mychaela Falconia src/libsys: pieced together from Citrine
2018-07-20 Mychaela Falconia components/main_ir: created for assembly modules
2018-07-20 Mychaela Falconia gcc/ld-script.src: additional polish
2018-07-20 Mychaela Falconia .../gcc/exceptions.S: added 2nd part that was missing in Citrine
2018-07-20 Mychaela Falconia linker script for gcc fw build: initial version put together
2018-07-20 Mychaela Falconia targets/*.m4 created for linker script generation in gcc version
2018-07-20 Mychaela Falconia created int_dummy.S with INT_*() functions for tcc.c
2018-07-20 Mychaela Falconia components/main: compile exceptions.S for gcc