log

age author description
Fri, 20 Jul 2018 20:44:02 +0000 Mychaela Falconia components/libsys_{fl,ir}: created
Fri, 20 Jul 2018 20:36:19 +0000 Mychaela Falconia src/libsys: pieced together from Citrine
Fri, 20 Jul 2018 20:22:38 +0000 Mychaela Falconia components/main_ir: created for assembly modules
Fri, 20 Jul 2018 19:36:25 +0000 Mychaela Falconia gcc/ld-script.src: additional polish
Fri, 20 Jul 2018 18:21:46 +0000 Mychaela Falconia .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Fri, 20 Jul 2018 17:33:14 +0000 Mychaela Falconia linker script for gcc fw build: initial version put together
Fri, 20 Jul 2018 09:38:01 +0000 Mychaela Falconia targets/*.m4 created for linker script generation in gcc version
Fri, 20 Jul 2018 07:36:23 +0000 Mychaela Falconia created int_dummy.S with INT_*() functions for tcc.c
Fri, 20 Jul 2018 06:51:54 +0000 Mychaela Falconia components/main: compile exceptions.S for gcc
Fri, 20 Jul 2018 06:46:56 +0000 Mychaela Falconia src/cs/system/main/gcc: asm code pieced from Citrine
Fri, 20 Jul 2018 06:12:21 +0000 Mychaela Falconia components/l1_int: compile l1_small_asm.S for gcc
Fri, 20 Jul 2018 05:56:58 +0000 Mychaela Falconia l1_small_asm.S: import from Citrine
Fri, 20 Jul 2018 05:51:53 +0000 Mychaela Falconia Nucleus gcc assembly modules compile
Fri, 20 Jul 2018 05:40:33 +0000 Mychaela Falconia src/nucleus/gcc: initial import from Citrine
Fri, 20 Jul 2018 03:49:01 +0000 Mychaela Falconia l1_trace.c: no memory copy checksum in the gcc-built version