log

age author description
Sat, 21 Jul 2018 00:22:35 +0000 Mychaela Falconia components/main_ir: ramvecs module now goes outside of libs
Sat, 21 Jul 2018 00:21:50 +0000 Mychaela Falconia gcc/makefile-body: created
Fri, 20 Jul 2018 23:39:27 +0000 Mychaela Falconia .../main/gcc/bootentry.S: the literal pool needs to be arranged
Fri, 20 Jul 2018 23:14:00 +0000 Mychaela Falconia src/cs/system/main/gcc/bootentry.S: written
Fri, 20 Jul 2018 20:53:45 +0000 Mychaela Falconia scripts/test-setup-tms470.sh: updated
Fri, 20 Jul 2018 20:44:02 +0000 Mychaela Falconia components/libsys_{fl,ir}: created
Fri, 20 Jul 2018 20:36:19 +0000 Mychaela Falconia src/libsys: pieced together from Citrine
Fri, 20 Jul 2018 20:22:38 +0000 Mychaela Falconia components/main_ir: created for assembly modules