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doc/Sniffing-workflow: document written
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 30 Aug 2023 03:03:04 +0000
parents f1c3dd2173d3
children 1068f9fd41d5
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f1c3dd2173d3 doc/Sniffing-hw-setup: document written
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1 The hardware setup for SIM sniffing with SIMtrace3 consists of the following
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2 components:
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3
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4 * The same SIMtrace FPC cables (going from a SIM socket to the 6-pin FPC
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5 connector) that were originally developed for SIMtrace1/2 and are sold by
f1c3dd2173d3 doc/Sniffing-hw-setup: document written
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6 Sysmocom;
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7
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8 * An off-the-shelf Lattice Icestick FPGA board (sold by Digi-Key, for example)
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9 that has been outfitted with header pins: the board ships with empty PTHs
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10 (plated through holes) at J1, hence a small soldering job is required to
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11 populate this header;
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12
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13 * Some in-between components described below.
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15 For the in-between components of the last bullet point above, there are 3
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16 possibilities, each described in its own section below.
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17
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18 HW setup version 0
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19 ==================
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20
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21 (works today)
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22
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23 The piece between the SIMtrace FPC cable from Sysmocom and the Icestick FPGA
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24 board is the "SIMtrace FPC passive connection" adapter (design files in
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25 boards/sim-fpc-pasv directory) from the fall of 2022. The electrical connection
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26 from the ME/ID SIM socket to the physical SIM is direct and physically
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27 continuous (no switches, no Heisenbugs), and a trio of FPGA I/O pins (configured
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28 as inputs) are connected directly to this SIM bus with jumper wires.
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29
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30 This hw setup is intended only as a very temporary prototype until we get hw
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31 setup version 1 described below. The present hw setup version 0 works ONLY if
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32 the ME/ID operates with class B voltage levels: if you try class A (5V), you'll
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33 instantly damage the FPGA by grossly exceeding its Absolute Maximum Ratings
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34 (don't do it!), and if you try class C (1.8V), the high level will fall right
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35 between Vil_max and Vih_min, causing the FPGA to receive garbage. However, this
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36 otherwise-unusable hw setup was good enough to prove the FPGA logic working,
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37 using an FCDEV3B as the ME/ID, manually forced into class B operation.
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38
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39 HW setup version 1
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40 ==================
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41
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42 (coming very soon)
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43
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44 Compared to hw setup version 0, one extra component is added between the
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45 sim-fpc-pasv adapter and the Icestick board: another little adapter board called
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46 "SIMtrace-ice multivolt sniffer", design files in boards/mv-sniffer directory.
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47 The only active component on the mv-sniffer board is a Nexperia 74LVC4T3144 dual
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48 supply logic voltage level translator IC, powered from SIM_VCC on its A side
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49 and from Icestick board +3.3V rail on its B side.
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50
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51 The mv-sniffer PCB is currently on its way to FreeCalypso HQ from the PCB fab
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52 in China, and once the PCB arrives, assembly will require another trip to
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53 Technotronix. Once we have this board assembled, we should have a working
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54 SIMtrace3 sniffing path that is fully compatible with all 3 voltage classes,
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55 per the original intent of SIMtrace3 project.
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56
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57 HW setup version 2
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58 ==================
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59
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60 (a little more distant, but will be needed before wider spread)
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61
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62 The solution with separate sim-fpc-pasv and mv-sniffer boards is expected to be
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63 quite inconvenient because of the number of pieces required - clutter on the lab
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64 bench - plus poor electrical design with jumper wires between the two boards
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65 extending the electrical length of the SIM bus before the LVC buffer. In the
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66 fully polished version of SIMtrace3, these two adapter boards will need to be
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67 combined into one. The final SIMtrace3 sniffer pod is expected to be a single
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68 board (still very simple and low cost) featuring the following components:
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69
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70 1) SIMtrace FPC connector
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71 2) SIM socket
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72 3) 74LVC4T3144 buffer IC
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73 4) SIM bus solidly connected between components 1, 2 and 3
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74 5) A header for FPGA board connection, wired to the 'B' side of component 3