FreeCalypso > hg > fc-sim-sniff

annotate fpga/tools/yosys-wrap @ 46:43f678895a3a

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simtrace3-sniff-rx: add some annotations to output
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 31 Aug 2023 10:01:40 +0000
parents af1a9732da1f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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18
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
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1 #!/bin/sh
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2
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3 if [ $# -lt 3 ]
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4 then
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5 echo "usage: $0 top-module json-output verilog-src..." 1>&2
af1a9732da1f FPGA build: include yosys-wrap in this repository
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6 exit 1
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7 fi
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8
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9 top="$1"
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10 json="$2"
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11
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12 shift
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13 shift
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14
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15 rm -f "$json"
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16 yosys -p "synth_ice40 -top $top -json $json" "$@"
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17
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18 if [ -f "$json" ]
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19 then
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20 echo "$json created, declaring success"
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21 exit 0
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22 else
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23 echo "$json NOT created, declaring error"
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24 exit 1
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25 fi