FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/Makefile @ 55:5268246520de

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simsniff-dec: decode command opcodes
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Oct 2023 00:20:05 +0000
parents cbfcc480d61b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 VSRC= clk_edge.v reset_detect.v sniff_rx.v sync_inputs.v top.v uart_tx.v
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990ecafdddb4 fpga tree: move icestick.pcf to common subdirectory
Mychaela Falconia <falcon@freecalypso.org>
parents: 19
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2 PCF= ../common/icestick.pcf
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 PROJ= fpga
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4
13
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
5 all: ${PROJ}.bin timing.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 ${PROJ}.json: ${VSRC}
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cbfcc480d61b fpga build: migrate to yosys-tee wrapper
Mychaela Falconia <falcon@freecalypso.org>
parents: 27
diff changeset
8 ../tools/yosys-tee top $@ synthesis.rpt ${VSRC}
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 ${PROJ}.asc: ${PROJ}.json ${PCF}
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
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d29dcfa78124 FPGA Makefile: generate pnr.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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12 --json ${PROJ}.json -l pnr.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 ${PROJ}.bin: ${PROJ}.asc
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 icepack $< $@
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16
13
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
17 timing.rpt: ${PROJ}.asc
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
18 icetime -d hx1k -mtr $@ $<
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
19
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 clean:
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e92ab75ce6a8 FPGA make clean: rm *.rpt too
Mychaela Falconia <falcon@freecalypso.org>
parents: 18
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21 rm -f *.json *.asc *.bin *.rpt