FreeCalypso > hg > fc-sim-sniff
annotate fpga/sniffer-basic/sniff_rx.v @ 14:54c3a277d64a
boards/mv-sniffer: PCB layout done
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 21 Aug 2023 03:02:01 +0000 |
parents | db8acc067542 |
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rev | line source |
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1 /* |
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2 * This Verilog module captures the ISO 7816-3 character sniffing receiver. |
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3 */ |
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4 |
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5 module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync, |
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6 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit); |
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7 |
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8 input IntClk; |
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9 input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync; |
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10 output Rx_strobe, Rx_error; |
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11 output [7:0] Rx_char; |
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12 output Rx_start_bit, Rx_parity_bit; |
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13 |
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14 wire SIM_CLK_edge; |
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15 |
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16 clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge); |
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17 |
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18 wire [9:0] etu_0p5, etu_1p0, etu_1p5; |
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19 |
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20 /* Fi/Di=372 only for now */ |
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21 assign etu_0p5 = 10'd185; |
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22 assign etu_1p0 = 10'd371; |
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23 assign etu_1p5 = 10'd557; |
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24 |
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25 reg rx_active; |
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26 reg [9:0] clk_count; |
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27 reg [3:0] bit_count; |
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28 reg [9:0] shift_reg; |
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29 |
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30 always @(posedge IntClk) |
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31 if (!SIM_RST_sync) |
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32 rx_active <= 1'b0; |
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33 else if (!rx_active && !SIM_IO_sync) |
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34 begin |
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35 rx_active <= 1'b1; |
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36 clk_count <= etu_0p5; |
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37 bit_count <= 4'd0; |
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38 end |
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39 else if (rx_active && SIM_CLK_edge) |
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40 begin |
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41 if (clk_count != 10'd0) |
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42 clk_count <= clk_count - 10'd1; |
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43 else begin |
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44 shift_reg <= {SIM_IO_sync,shift_reg[9:1]}; |
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45 bit_count <= bit_count + 4'd1; |
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46 if (bit_count == 4'd9) |
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47 clk_count <= etu_1p5; |
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48 else |
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49 clk_count <= etu_1p0; |
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50 if (bit_count == 4'd10) |
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51 rx_active <= 1'b0; |
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52 end |
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53 end |
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54 |
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55 assign Rx_strobe = rx_active && SIM_CLK_edge && clk_count == 10'd0 && |
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56 bit_count == 4'd10; |
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57 assign Rx_error = Rx_strobe && !SIM_IO_sync; |
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58 assign Rx_char = shift_reg[8:1]; |
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59 assign Rx_start_bit = shift_reg[0]; |
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60 assign Rx_parity_bit = shift_reg[9]; |
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61 |
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62 endmodule |