FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/uart_tx.v @ 14:54c3a277d64a

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
boards/mv-sniffer: PCB layout done
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 03:02:01 +0000
parents 7db5fd6646df
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This Verilog module captures the UART output logic.
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 */
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 module uart_tx (IntClk, Tx_trigger, Tx_data, UART_out);
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 input IntClk;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 input Tx_trigger;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 input [15:0] Tx_data;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 output UART_out;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 reg UART_out;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 reg tx_active;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 reg [1:0] clk_div;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 reg [4:0] bit_count;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 reg [17:0] shift_reg;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 initial begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 tx_active = 1'b0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 UART_out = 1'b1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 if (!tx_active && Tx_trigger)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 tx_active <= 1'b1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 UART_out <= 1'b0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 clk_div <= 2'd0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 shift_reg <= {Tx_data[15:8],2'b01,Tx_data[7:0]};
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 bit_count <= 5'd0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 else if (tx_active)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 clk_div <= clk_div + 2'd1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 if (clk_div == 2'd3)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 UART_out <= shift_reg[0];
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 shift_reg <= {1,shift_reg[17:1]};
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 bit_count <= bit_count + 5'd1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 if (bit_count == 5'd19)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 tx_active <= 1'b0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 endmodule