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annotate doc/PPS-catcher-FSM @ 47:7c9bf72d460f

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author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 21 Sep 2023 05:00:50 +0000
parents c2fc75655937
children 1068f9fd41d5
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34
c2fc75655937 doc/PPS-catcher-FSM: it has been implemented
Mychaela Falconia <falcon@freecalypso.org>
parents: 24
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1 This document describes the PPS catcher state machine that has been implemented
c2fc75655937 doc/PPS-catcher-FSM: it has been implemented
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parents: 24
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2 in the SIMtrace3 sniffer FPGA, using a sort of verbal pseudocode.
24
f1e7795557b1 doc/PPS-catcher-FSM: initial description
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3
f1e7795557b1 doc/PPS-catcher-FSM: initial description
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4 INITIAL:
f1e7795557b1 doc/PPS-catcher-FSM: initial description
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5
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6 This state will be entered upon reset (held in this state while RST is low).
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7 Must receive 8'h3B to proceed to state T0, otherwise transition to DONE.
f1e7795557b1 doc/PPS-catcher-FSM: initial description
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8
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9 ATR_T0:
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10
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11 Whatever byte we receive in this state, we latch the upper nibble in the Y
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12 register and the lower nibble in the K register - then proceed to TAn.
f1e7795557b1 doc/PPS-catcher-FSM: initial description
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13
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14 ATR_TAn:
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15
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16 Advance to TBn if Y register indicates no TAn OR we got a byte.
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17
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18 ATR_TBn:
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19
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20 Advance to TCn if Y register indicates no TBn OR we got a byte.
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21
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22 ATR_TCn:
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23
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24 Advance to TDn if Y register indicates no TCn OR we got a byte.
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25
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26 ATR_TDn:
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27
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28 If Y register indicates no TDn, advance to state ATR_HIST.
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29
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30 ELSE wait for byte; upon byte Rx, do the following:
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31
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32 - latch the upper nibble in the Y register;
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33 - if lower nibble != 0, set TCK present flag;
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34 - always go back to TAn.
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35
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36 ATR_HIST:
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37
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38 If K == 0, advance to state ATR_TCK.
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39
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40 ELSE wait for byte; upon byte Rx, decrement K and remain in this state.
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41
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42 ATR_TCK:
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43
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44 Advance to READY_FOR_PPS if Have_TCK flag is false OR we got a byte.
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45
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46 READY_FOR_PPS:
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47
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Mychaela Falconia <falcon@freecalypso.org>
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48 Wait for Rx byte. If the byte equals 8'hFF, proceed to REQ_PPS0,
f1e7795557b1 doc/PPS-catcher-FSM: initial description
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49 otherwise DONE.
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50
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51 REQ_PPS0:
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52
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53 Wait for Rx byte; latch 3 bits of the received byte and proceed to REQ_PPS1.
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54
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55 REQ_PPS1:
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56
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57 Advance to REQ_PPS2 if register indicates no PPS1 OR we got a byte.
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58
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59 REQ_PPS2:
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60
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61 Advance to REQ_PPS3 if register indicates no PPS2 OR we got a byte.
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62
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63 REQ_PPS3:
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64
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65 Advance to REQ_PCK if register indicates no PPS3 OR we got a byte.
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66
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67 REQ_PCK:
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68
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69 Wait for Rx byte; ignore the received value and go to READY_FOR_RESP.
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70
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71 READY_FOR_RESP:
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72
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73 Wait for Rx byte. If the byte equals 8'hFF, proceed to RESP_PPS0,
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74 otherwise DONE.
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75
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76 RESP_PPS0:
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77
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78 Wait for Rx byte. If PPS1 indicator bit is cleared, go to DONE. Otherwise,
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79 latch the 3 bits like in REQ_PPS0 and proceed to RESP_PPS1.
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80
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81 RESP_PPS1:
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82
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83 Wait for Rx byte. The upper 6 bits must match 6'b100101 - if mismatch, go to
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84 DONE. If the upper bits match, latch the two lsbs - they will be the speed
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85 enhancement multiplier bits - and proceed to RESP_PPS2.
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86
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87 RESP_PPS2:
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88
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89 Advance to RESP_PPS3 if register indicates no PPS2 OR we got a byte.
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90
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91 RESP_PPS3:
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92
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93 Advance to RESP_PCK if register indicates no PPS3 OR we got a byte.
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94
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95 RESP_PCK:
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96
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97 Wait for Rx byte. Upon getting this final byte, trigger the speed enhancement
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98 switch and go to DONE.
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99
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100 DONE:
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101
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102 Final state, nothing more happens.