FreeCalypso > hg > fc-sim-sniff

annotate README @ 8:7cab8e0dd937

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FPGA Makefile: yosys-wrap installed on Mother's system
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 00:55:33 +0000
parents fbbafa93b52b
children 510bef2b2000
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1 Alternative implementation of SIMtrace idea,
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2 using iCE40 FPGA instead of AT91SAMx
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3 ============================================
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4
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5 Q: What is the principal idea behind SIMtrace, as distinct from the specific
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6 implementation realized by "standard" Osmocom SIMtrace?
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7
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8 A: The two principal objectives of SIMtrace are:
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9
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10 1) Passive sniffing of communication between a phone-type device and a SIM,
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11 ideally as transparent and non-invasive as possible.
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12
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13 2) Card emulation: the SIMtrace apparatus presents itself to the phone (or
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14 modem or other phone-type device) as a SIM, either emulating the entire
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15 SIM CardOS functionality in software or communicating with a real SIM
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16 located somewhere remotely, across the Internet.
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17
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18 Q: What are the shortcomings of the existing Osmocom SIMtrace implementation of
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19 the above goals?
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20
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21 A: In the opinion of Mother Mychaela of FreeCalypso, the electrical aspects of
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22 Osmocom SIMtrace implementation are its biggest shortcoming. The following
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23 problems are most acute currently:
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24
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25 * Current SIMtrace v2 hardware is not 5V-tolerant: connecting this apparatus to
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26 an old phone that puts out 5V (class A) on its SIM socket can damage the
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27 hardware, as class A SIM voltages exceed the absolute maximum rating spec of
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28 the AT91SAM3S4B microcontroller on the SIMtrace v2 board, which is connected
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29 directly to the SIM bus.
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30
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31 * One option would be to revive the previous hardware generation as in SIMtrace
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32 v1, replacing the AT91SAM3S with AT91SAM7S. However, all firmware maintained
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33 by Osmocom is written for SAM3S only, thus a backport to SAM7S would involve
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34 significant work. Given that the resulting solution would still be far from
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35 my idea of perfection, I find it difficult to justify investing in that
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36 software effort - instead I would rather work on a more philosophically-proper
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37 solution.
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38
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39 * AT91SAMx-based SIMtrace, both v1 and v2, works (most of the time, but not 100%
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40 reliably) with 1.8V phone-SIM combination (a phone that prefers class C and a
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41 SIM that supports it) only by accident. The Vih spec (the minimum required
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42 voltage on a signal line for it to register reliably as a 1) is 2.0 V for
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43 AT91SAM7S or 2.31 V (0.7 * Vddio, Vddio = 3.3 V) for AT91SAM3S, but the actual
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44 voltage on SIM interface lines in class C operation will never rise above
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45 1.8 V. The electrical interface on this hw operates severely out of spec,
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46 and I find it rather miraculous that it works at all. Not surprisingly,
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47 reports are starting to trickle in with user experiences of it actually NOT
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48 working sometimes.
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49
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50 * Even if the SIM interface is restricted (by the phone, by the SIM, or by
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51 SIMtrace MITM function tampering with ATR or file characteristics bytes) to
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52 operating in class B (3.0 V nominal) only, the existing AT91SAMx SIMtrace
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53 boards are still electrically unclean. Looking at the schematics, one can see
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54 that both CLK and I/O lines are pulled up (with resistors) to the SIMtrace
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55 board's 3.3V rail, which is a higher voltage that what the phone will put out
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56 (3.0 V or 1.8 V), and in the case of SIMtrace v1 with a 5V phone, that pull-up
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57 will turn into a pull-midway-down instead.
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58
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59 * My philosophy is that the tracing apparatus should be making only a high-
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60 impedance connection to the SIM bus and nothing more, while the SIM bus itself
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61 is galvanically connected from the phone to the physical SIM without passing
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62 through any switches or other potential Heisenbug-inducing artifacts.
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63
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64 My first thought was to gently modify the existing AT91SAMx-based SIMtrace
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65 design for electrically clean multivolt operation:
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66
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67 * Replace the electrical switches for SIM VCC (FPF2109) and SIM RST/CLK/IO
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68 (CB3Q3244) with either a relay (my initial thought, but way too power-hungry)
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69 or a manually operated 5PDT slide switch;
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70
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71 * Insert a Nexperia 74LVC4T3144 dual-supply buffer between the SIM bus and the
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72 MCU, providing a sniffing path that not only supports all 3 voltage classes,
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73 but is electrically clean, making only a high-impedance connection to the SIM
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74 bus as I desire;
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75
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76 * Connect a 74LVC1G07 open drain driver (fed with TxD from the MCU) to the SIM
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77 bus I/O line, providing a signal path for card emulation mode. (In trace mode
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78 the firmware would be responsible for never turning on this OD driver, keeping
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79 the tracing apparatus High-Z.)
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80
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81 However, as I was reading AT91SAMx datasheets more carefully in preparation for
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82 embarking on a project to turn the above idea into reality, I saw a big problem:
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83 when the USART is put into ISO 7816-3 mode, it uses the chip's TxD pin (switched
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84 to open drain operation) for both Rx and Tx, and there is no option to keep
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85 separate RxD and TxD pins with an external receiving buffer and an external OD
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86 driver.
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87
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88 It would probably be possible to build an all-voltage SIM interface with
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89 AT91SAMx, perhaps by using one of those bidirectional level shifter ICs that
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90 somehow automagically handle driving direction reversals. But I personally am
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91 not too inclined to trust those automagical bidirectional translators, they
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92 just don't align with my design philosophy - I would much much rather have
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93 unidirectional buffers, one for sniffing and another for OD-driving the I/O
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94 line in card emulation mode. Seeing that AT91SAMx is incompatible with such
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95 electrical design, I decided to screw AT91SAMx and go for a radically different
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96 approach.
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97
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98 Outline of FPGA-based alternative design
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99 ========================================
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100
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101 My (Mother Mychaela's) idea of alternative SIMtrace implementation consists of
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102 the following pieces:
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103
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104 1) The passive SIMtrace FPC connection board (boards/sim-fpc-pasv) is a trivial
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105 PCB that electrically interconnects a SIM socket, an FPC connection for
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106 SIMtrace FPC cables and a set of 2.54 mm header pins bringing out all SIM
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107 interface signals.
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108
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109 2) A second little adapter board (tentatively named mv-sniffer) will feature one
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110 active component, but will still be just as trivial: it will be a PCB hosting
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111 a single 74LVC4T3144 IC, with 2.54 mm header pins for the SIM side (SIM VCC
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112 will go to the buffer IC's VccA) and for the FPGA board side; a power rail
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113 from the latter board will go to the buffer IC's VccB.
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114
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115 3) The FPGA board will be an off-the-shelf item, eliminating the major hurdle
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116 of having to design and build a custom board of substantial complexity. My
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117 first attempt will be to use the Icestick board with iCE40HX1K FPGA; if this
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118 FPGA proves to be too small, I will then look for another suitable board
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119 with a bigger FPGA.
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120
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121 The Icestick board features not only the HX1K FPGA, but also an FT2232H chip
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122 handling the USB interface. FT2232H channel A is for FPGA programming, but
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123 channel B is a regular UART, connected with PCB traces to FPGA I/O pins for
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124 user logic. The logic implemented in the FPGA will use this UART interface to
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125 communicate with higher-level software, which will be implemented as simple
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126 userspace programs - thus there is no "firmware" component per se.
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127
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128 In terms of FPGA gateware functionality, the passive sniffer function will be
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129 implemented first; once it works, a different logic design will be implemented
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130 for card emulation mode.
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131
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132 In terms of hardware as in boards, the first prototype version will use separate
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133 sim-fpc-pasv and mv-sniffer boards, connected with jumper wires between 2.54 mm
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134 header pins. Because the signals carried by these jumper wires reside on the
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135 "target" SIM bus side of the buffer, these wires add more than just clutter -
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136 they also add to the electrical length of the external SIM bus, which is
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137 obviously bad. Once the basic design is proven good, I plan to spin out another
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138 simple board that will feature the SIM socket, the SIMtrace FPC connector, the
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139 74LVC4T3144 buffer and a header for connecting to the FPGA board. Because the
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140 latter connection resides past the buffer, wire length here does NOT add to the
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141 SIM bus.
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142
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143 All of the just-described hardware config is for tracing only, not for card
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144 emulation. For the latter function yet another, albeit still very simple,
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145 adapter board will need to be made. The cardem adapter board will feature the
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146 SIMtrace FPC connector, two active ICs (74LVC4T3144 receiving buffer and
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147 74LVC1G07 OD driver) and the header for connecting to the FPGA board. Note the
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148 absence of a SIM socket - hardware setups for sniffing a phone's communication
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149 with a real SIM on the one hand and for running with a software-emulated SIM on
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150 the other hand are different, and it does no good trying to combine them.