FreeCalypso > hg > fc-sim-sniff
annotate fpga/sniffer-pps/spenh_ctrl.v @ 58:95ed46b5f8f1 default tip
doc/Sniffing-hw-setup: mv-sniffer is here
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 04 Oct 2023 05:55:09 +0000 |
parents | ab37fcb71744 |
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fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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1 /* |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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2 * This module implements speed enhancement control based on signals |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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3 * from the PPS catcher block. |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
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4 */ |
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Mychaela Falconia <falcon@freecalypso.org>
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5 |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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6 module spenh_ctrl (IntClk, SIM_RST_sync, Rx_strobe, Rx_char, |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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7 pos_PPS_resp_PPS1, pos_PPS_resp_PCK, |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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8 speed_enh_mode, speed_enh_mult); |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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9 |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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10 input IntClk; |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 input SIM_RST_sync; |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 input Rx_strobe; |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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13 input [7:0] Rx_char; |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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14 input pos_PPS_resp_PPS1, pos_PPS_resp_PCK; |
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Mychaela Falconia <falcon@freecalypso.org>
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15 |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
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16 output reg speed_enh_mode; |
ab37fcb71744
fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
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17 output reg [1:0] speed_enh_mult; |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
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18 |
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Mychaela Falconia <falcon@freecalypso.org>
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19 always @(posedge IntClk) |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
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20 if (!SIM_RST_sync) |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
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21 speed_enh_mode <= 1'b0; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 else if (Rx_strobe && pos_PPS_resp_PCK) |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 speed_enh_mode <= 1'b1; |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 |
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Mychaela Falconia <falcon@freecalypso.org>
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25 always @(posedge IntClk) |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 if (Rx_strobe && pos_PPS_resp_PPS1) |
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Mychaela Falconia <falcon@freecalypso.org>
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27 speed_enh_mult <= Rx_char[1:0]; |
ab37fcb71744
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Mychaela Falconia <falcon@freecalypso.org>
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28 |
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Mychaela Falconia <falcon@freecalypso.org>
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29 endmodule |