FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/sniff_rx.v @ 56:966a54303d68

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
simsniff-dec: factor out high-level decoding
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Oct 2023 01:18:50 +0000
parents ab37fcb71744
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This Verilog module captures the ISO 7816-3 character sniffing receiver.
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 */
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
31
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
6 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit,
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
7 speed_enh_mode, speed_enh_mult);
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 input IntClk;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 output Rx_strobe, Rx_error;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 output [7:0] Rx_char;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 output Rx_start_bit, Rx_parity_bit;
31
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
14 input speed_enh_mode;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
15 input [1:0] speed_enh_mult;
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 wire SIM_CLK_edge;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20
31
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
21 reg [9:0] etu_0p5, etu_1p0, etu_1p5; /* combinational */
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22
31
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
23 always @*
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
24 casez ({speed_enh_mode,speed_enh_mult})
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
25 3'b0??:
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
26 begin
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
27 /* F/D = 372 */
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
28 etu_0p5 = 10'd185;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
29 etu_1p0 = 10'd371;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
30 etu_1p5 = 10'd557;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
31 end
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
32 3'b100:
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
33 begin
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
34 /* F/D = 64 */
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
35 etu_0p5 = 10'd31;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
36 etu_1p0 = 10'd63;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
37 etu_1p5 = 10'd95;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
38 end
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
39 3'b101:
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
40 begin
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
41 /* F/D = 32 */
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
42 etu_0p5 = 10'd15;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
43 etu_1p0 = 10'd31;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
44 etu_1p5 = 10'd47;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
45 end
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
46 3'b110:
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
47 begin
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
48 /* F/D = 16 */
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
49 etu_0p5 = 10'd7;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
50 etu_1p0 = 10'd15;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
51 etu_1p5 = 10'd23;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
52 end
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
53 3'b111:
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
54 begin
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
55 /* F/D = 8 */
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
56 etu_0p5 = 10'd3;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
57 etu_1p0 = 10'd7;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
58 etu_1p5 = 10'd11;
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
59 end
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
60 endcase
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62 reg rx_active;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 reg [9:0] clk_count;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 reg [3:0] bit_count;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 reg [9:0] shift_reg;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 if (!SIM_RST_sync)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 rx_active <= 1'b0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 else if (!rx_active && !SIM_IO_sync)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 rx_active <= 1'b1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73 clk_count <= etu_0p5;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 bit_count <= 4'd0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 else if (rx_active && SIM_CLK_edge)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 if (clk_count != 10'd0)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 clk_count <= clk_count - 10'd1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80 else begin
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81 shift_reg <= {SIM_IO_sync,shift_reg[9:1]};
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
82 bit_count <= bit_count + 4'd1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 if (bit_count == 4'd9)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 clk_count <= etu_1p5;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85 else
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86 clk_count <= etu_1p0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87 if (bit_count == 4'd10)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
88 rx_active <= 1'b0;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
89 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
90 end
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
91
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
92 assign Rx_strobe = rx_active && SIM_CLK_edge && clk_count == 10'd0 &&
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
93 bit_count == 4'd10;
10
db8acc067542 fpga/sniffer-basic/sniff_rx.v: typo in signal name
Mychaela Falconia <falcon@freecalypso.org>
parents: 6
diff changeset
94 assign Rx_error = Rx_strobe && !SIM_IO_sync;
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
95 assign Rx_char = shift_reg[8:1];
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96 assign Rx_start_bit = shift_reg[0];
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
97 assign Rx_parity_bit = shift_reg[9];
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
98
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
99 endmodule