FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/top.v @ 31:ab37fcb71744

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fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
parents dc99c9962aed
children
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7db5fd6646df fpga/sniffer-basic: initial version
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1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
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2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST_in, SIM_CLK_in,
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3 SIM_IO_in, SIM_IO_out);
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5 input CLK12;
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6 output LED1, LED2, LED3, LED4, LED5;
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8 input UART_TxD, UART_RTS, UART_DTR;
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9 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
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11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
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12 output SIM_IO_out;
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14 /* input synchronizers */
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16 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
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18 sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
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19 SIM_IO_in, SIM_IO_sync);
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21 /* character receiver */
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23 wire Rx_strobe, Rx_error;
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24 wire [7:0] Rx_char;
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25 wire Rx_start_bit, Rx_parity_bit;
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27 sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
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28 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
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30 /* explicit detection of RST transitions */
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32 wire SIM_RST_toggle;
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34 reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);
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36 /* output to the host */
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38 wire Tx_trigger;
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39 wire [15:0] Tx_data;
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41 assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
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42 assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,3'b000,
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43 Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};
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45 uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);
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47 /* UART modem control outputs: unused */
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49 assign UART_CTS = 1'b1;
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50 assign UART_DSR = 1'b0;
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51 assign UART_DCD = 1'b0;
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53 /* board LEDs */
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55 assign LED1 = 1'b1;
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56 assign LED2 = 1'b0;
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57 assign LED3 = 1'b1;
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58 assign LED4 = 1'b0;
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59 assign LED5 = SIM_RST_in;
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61 /* SIM_IO_out dummy: if someone mistakenly connects an Icestick board with
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62 * this FPGA image in it to a cardem pod instead of the sniffing one,
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63 * we ensure that the 74LVC1G07 OD buffer remains off by feeding logic HIGH
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64 * to this buffer.
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65 */
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67 assign SIM_IO_out = 1'b1;
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69 endmodule