FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/sync_inputs.v @ 18:af1a9732da1f

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FPGA build: include yosys-wrap in this repository
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 19:25:35 +0000
parents 7db5fd6646df
children
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1 /*
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2 * This Verilog module captures the input synchronizer logic: passing all 3
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3 * SIM sniffer inputs through double-DFF synchronizers to bring them into
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4 * our internal clock domain.
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5 */
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7 module sync_inputs (IntClk, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
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8 SIM_IO_in, SIM_IO_sync);
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10 input IntClk;
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11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
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12 output SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
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13 reg SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
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15 reg SIM_RST_sync1, SIM_CLK_sync1, SIM_IO_sync1;
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17 always @(posedge IntClk)
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18 SIM_RST_sync1 <= SIM_RST_in;
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20 always @(posedge IntClk)
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21 SIM_RST_sync <= SIM_RST_sync1;
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23 always @(posedge IntClk)
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24 SIM_CLK_sync1 <= SIM_CLK_in;
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26 always @(posedge IntClk)
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27 SIM_CLK_sync <= SIM_CLK_sync1;
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29 always @(posedge IntClk)
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30 SIM_IO_sync1 <= SIM_IO_in;
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32 always @(posedge IntClk)
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33 SIM_IO_sync <= SIM_IO_sync1;
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34
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35 endmodule