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annotate boards/mv-sniffer/src/ic_74LVC4T3144.v @ 4:b275c69c1b80

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doc: describe proposed FPGA design
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 29 Jul 2023 07:06:54 +0000
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Mychaela Falconia <falcon@freecalypso.org>
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1 module ic_74LVC4T3144 (GND, VccA, VccB, nOE, A1, A2, A3, YA4,
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2 YB1, YB2, YB3, B4);
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3
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4 input GND, VccA, VccB;
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5 input nOE;
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6 input A1, A2, A3, B4;
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7 output YB1, YB2, YB3, YA4;
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9 /* instantiate the package; the mapping of signals to pins is defined here */
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11 pkg_TSSOP14 pkg (.pin_1(VccA),
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12 .pin_2(A1),
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13 .pin_3(A2),
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14 .pin_4(A3),
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15 .pin_5(YA4),
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16 .pin_6(GND),
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17 .pin_7(GND),
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18 .pin_8(B4),
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19 .pin_9(), /* no connect */
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20 .pin_10(YB3),
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21 .pin_11(YB2),
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22 .pin_12(YB1),
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23 .pin_13(VccB),
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24 .pin_14(nOE)
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25 );
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26
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27 endmodule