FreeCalypso > hg > fc-sim-sniff

annotate fpga/tools/yosys-wrap @ 34:c2fc75655937

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
doc/PPS-catcher-FSM: it has been implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 22:58:26 +0000
parents af1a9732da1f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
18
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 #!/bin/sh
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 if [ $# -lt 3 ]
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 then
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 echo "usage: $0 top-module json-output verilog-src..." 1>&2
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 exit 1
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 fi
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 top="$1"
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 json="$2"
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 shift
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 shift
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 rm -f "$json"
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 yosys -p "synth_ice40 -top $top -json $json" "$@"
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 if [ -f "$json" ]
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 then
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 echo "$json created, declaring success"
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 exit 0
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 else
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 echo "$json NOT created, declaring error"
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 exit 1
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 fi