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annotate doc/Sniffer-FPGA-design @ 52:cbfcc480d61b

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fpga build: migrate to yosys-tee wrapper
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 03 Oct 2023 18:17:58 +0000
parents 1068f9fd41d5
children
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1 FPGA component of FreeCalypso SIMsniff
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2 ======================================
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4 The present FreeCalypso solution for SIM interface sniffing consists of a
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5 sniffer pod (hardware adapter with level shifters) and a Lattice Icestick FPGA
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6 board, loaded with the appropriate gateware image from the present project.
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7 This document describes the design and operation of the FPGA component of
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8 FC SIMsniff.
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10 Hardware architecture and FPGA design principle
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11 ===============================================
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13 The two principal components of the Icestick board are an iCE40HX1K FPGA and an
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14 FT2232H-based USB host interface. Our sniffer logic function in the FPGA
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15 operates principally as a byte forwarder from the ISO 7816-3 sniffer block to
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16 the FT2232H UART: every time the bus sniffer block captures a character (in ISO
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17 7816-3 terminology) being passed on the SIM electrical interface in either
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18 direction (the two directions of transmission are indistinguishable to a tap
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19 sniffer that does not actively participate in the protocol), the FPGA forwards
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20 this character to the connected host computer (by way of FT2232H UART) for
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21 further processing in software. The UART data line going from the FPGA to the
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22 FT2232H is the sole functional output from this FPGA, aside from some
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23 non-essential LED outputs: right now the green LED shows the current state of
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24 SIM RST line, and we might add another LED showing if SIM CLK is running or
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25 stopped. The other UART data line going the opposite direction (output from
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26 FT2232H) remains unused in this application, i.e., the host software application
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27 will only read/receive from the ttyUSBx FPGA device and won't send anything to
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28 it. All modem control lines on this UART interface likewise remain unused.
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30 Serial interface format
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31 =======================
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33 For every ISO 7816-3 character captured by the sniffer, two back-to-back UART
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34 bytes are transferred from the FPGA to the host computer; more generally, the
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35 FPGA can only transmit pairs of back-to-back bytes on this UART and no
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36 singletons or other arrangements - thus the host receiver can always recover
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37 synchronization by dropping any partially received two-byte message (the first
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38 byte of an expected pair) during prolonged pauses. The FPGA transmits the two
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39 back-to-back UART bytes as a single shift-out of 20 bits, conveying two bytes
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40 in 8N1 framing.
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42 Why are we turning every captured ISO 7816-3 character into a pair of bytes on
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43 our internal UART interface, why not simply forward it as a single byte? The
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44 reason is that we need to pass some additional bits beyond the 8 that comprise
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45 the ISO 7816-3 character payload; the additional bits which we need to pass are
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46 as follows:
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47
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48 - the received parity bit;
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49 - a flag indicating whether or not an error signal (ISO 7816-3 section 7.3)
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50 was seen;
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51 - additional flag bits communicating SIM RST assertion and negation events,
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52 as distinct from ISO 7816-3 characters;
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53 - additional flags indicating actions of the integrated PPS catcher state
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54 machine, to be described later in this document.
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56 Assertion or negation of SIM RST is the only other possible event (besides ISO
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57 7816-3 character capture, with or without attendant PPS catcher state machine
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58 action) that can cause the FPGA to send a byte-pair UART message to the host
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59 computer. One bit in the 16-bit message will distinguish between characters
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60 and RST events, another bit will indicate the state of RST at the time of the
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61 event (new RST for transitions, 1 for characters), and all other bits are
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62 meaningful only for characters.
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63
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64 Detailed serial interface format
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65 --------------------------------
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67 Treating the two transmitted bytes as a single 16-bit word, with the least
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68 significant 8 bits transmitted first (matching the transmission order of bits
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69 within a byte, see IEN 137), the 16 bits of this word are assigned as follows:
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71 Bit 15: set to 0 if this message signals ISO 7816-3 character reception or 1 if
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72 it signals a change of state in the RST line.
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74 Bit 14: new state of RST in the case of RST state change messages; should always
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75 be 1 in character Rx messages.
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76
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77 The remaining bits are valid only in character Rx messages:
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78
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79 Bit 13: set to 0 if this character was captured in F/D=372 mode or 1 if it was
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80 captured in one of the supported speed enhancement modes (F=512, D=8/16/32/64).
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81
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82 Bit 12: set to 1 in the byte position that is expected to be the final PCK byte
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83 of the card's PPS response in the case of supported speed enhancement modes,
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84 0 otherwise.
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85
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86 Bit 11: set to 1 in the byte position that is expected to be the PPS1 byte of
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87 the card's PPS response, 0 otherwise.
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88
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89 Bit 10: set to 1 if the error signal of ISO 7816-3 section 7.3 was detected,
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90 0 otherwise.
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91
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92 Bit 9: sampled line value at the midpoint of the start bit, should be 0 in a
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93 properly working system.
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94
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95 Bit 8: received parity bit;
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96
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97 Bits [7:0]: payload bits of the received character.
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98
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99 UART baud rate
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100 ==============
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101
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102 The baud rate on the UART interface between the FPGA and the FT2232H converter
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103 is 3000000 bps. This high (and very non-RS232-standard) UART baud rate was
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104 chosen for the following reasons:
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105
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106 * Our UART interface is totally private, going nowhere but the on-board FT2232H,
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107 thus it doesn't matter if the baud rate is standard-ish or totally
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108 non-standard.
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109
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110 * No cables of any kind are used, instead the UART interface is confined to
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111 short PCB traces running between the FPGA and the FTDI chip on the same board
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112 - hence high baud rates are not a problem.
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113
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114 * Our UART baud rate needs to be high enough to provide good margin, despite
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115 our 2x expansion, at the highest possible effective bps rate on the SIM
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116 interface, meaning the highest possible SIM CLK frequency and the most
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117 aggressive F/D ratio. The combination of SIM CLK at 5 MHz, F=512 and D=64
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118 corresponds to 625000 bps effective on the SIM interface; running our UART at
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119 3 Mbps provides sufficient margin.
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120
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121 Clocking design
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122 ===============
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123
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124 The FPGA on the Icestick board receives a 12 MHz clock input. Our original
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125 plan was to use the FPGA's on-chip PLL to multiply this clock by 4, producing a
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126 48 MHz system clock - however, this plan has been shelved for now, and our
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127 current sniffer design uses the 12 MHz clock directly as its system clock.
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128
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129 The 3 inputs to the FPGA coming from the SIM electrical sniffer (buffered and
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130 level-shifted SIM RST, CLK and I/O lines) pass through two cascaded DFFs,
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131 bringing them into our internal clock domain. The delay added by these cascaded
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132 DFFs is not a concern: we are a passive sniffer without any output back to the
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133 SIM interface, and all 3 signal inputs will be subject to the same delay.
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134
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135 As stated in the previous section, the baud rate on the UART interface between
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136 the FPGA and the FT2232H converter is 3000000 bps. The UART output block in
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137 the FPGA uses a simple /4 divider from CLK12 (board-level 12 MHz clock input)
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138 to time its output bits; the original intent was to use a /16 divider from
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139 48 MHz SYSCLK.
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140
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141 ISO 7816-3 sniffer block
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142 ========================
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143
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144 Our ISO 7816-3 receiver triggers on the falling edge of the I/O line. Once it
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145 detects a high-to-low transition on the SYSCLK-synchronized SIM_IO input, it
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146 starts counting SIM CLK cycles - we are arbitrarily choosing low-to-high
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147 transition of SYSCLK-synchronized SIM_CLK input as the trigger point. (This
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148 choice is arbitrary because per the spec there is no defined phase relation
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149 between SIM CLK and SIM I/O transitions.)
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150
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151 Our ISO 7816-3 receiver needs to know how many SIM CLK cycles constitute one
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152 etu - or more precisely, our sniffing receiver needs to know how many SIM CLK
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153 cycles constitute 0.5 etu, 1 etu and 1.5 etu, in order to locate various needed
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154 sampling points relative to the instant at which SIM_IO was initially sampled
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155 low. Our sniffer-pps FPGA supports the following combinations:
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156
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157 F=372, D=1: 372 clocks per etu
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158 F=512, D=8: 64 clocks per etu
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159 F=512, D=16: 32 clocks per etu
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160 F=512, D=32: 16 clocks per etu
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161 F=512, D=64: 8 clocks per etu
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162
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163 Our sniffing Rx is held down in reset (won't receive anything) while SIM RST is
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164 low; as we come out of reset upon SIM RST line going high, our sniffing Rx is in
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165 F/D=372 mode and the PPS catcher state machine is set to its initial state. As
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166 ISO 7816-3 characters captured in this F/D=372 mode are received, our PPS
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167 catcher state machine follows the spec-defined structure of ATR to locate its
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168 end. If the end of ATR is followed by a PPS request which is then followed by
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169 a PPS response, and if the PPS response from the card includes a PPS1 byte that
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170 invokes one of our supported speed enhancement modes listed above, the sniffing
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171 receiver's notion of etu length is switched at the correct point in time:
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172 immediately after finishing RX of the PCK byte that concludes the card's PPS
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173 response.
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174
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175 Direct and inverse coding conventions
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176 =====================================
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177
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178 Only the card and not the interface device (ISO 7816-3 terminology) determines
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179 which coding convention is used, direct or inverse. So far we (FreeCalypso)
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180 have not yet encountered a real-life SIM that uses the inverse convention, only
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181 the direct convention kind. The approach taken in FC SIMsniff is that the FPGA
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182 is mostly (except for the integrated PPS catcher) oblivious to the coding
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183 convention: it passes the 9 received bits (8 data bits and 1 parity bit) to the
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184 16-bit UART message as-is, without inverting or reordering them. The coding
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185 convention and the parity check are then handled in simsniff-dec host
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186 application.
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187
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188 Integrated PPS catcher
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189 ======================
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190
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191 Our sniffer FPGA logic was developed incrementally. The first version,
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192 preserved in fpga/sniffer-basic in case we ever need to revisit it, uses an ISO
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193 7816-3 sniffing Rx block with fixed F/D ratio of 372. That simple version is
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194 sufficient for sniffing exchanges between a GSM ME and a SIM *if* the etu-
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195 defining F/D ratio is never switched from the basic default of 372, either
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196 because the SIM does not support speed enhancement or because the ME does not
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197 support such. However, such no-speed-enhancement scenarios are rare:
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198
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199 * All commercial operators' SIMs in the present era do support speed
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200 enhancement, and so do our own FCSIM1 cards. More specifically, our FCSIM1
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201 model supports F=512 D=8, while most commercial operators' SIMs that have
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202 passed through Mother's hands (plus sysmoUSIM-SJS1 and sysmoISIM-SJA2)
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203 support F=512 D=32.
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204
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205 * F=512 D=8 is a speed enhancement mode endorsed by the most classic GSM 11.11
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206 spec, and it is supported by classic GSM ME implementations including our dear
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207 Calypso.
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208
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209 As a result of the above two factors, most real-life GSM ME to SIM sessions
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210 which we will need to sniff and trace in the course of Vintage Mobile Phone
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211 debugging and support will include a PPS exchange switching from F/D=372 to a
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212 smaller number of SIM CLK cycles per etu, specifically one of F=512 D=8/16/32/64
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213 modes.
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214
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215 The main difficulty with capturing SIM interface sessions that use speed
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216 enhancement is as follows: in order for the session capture to be complete,
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217 without any lost bits, the sniffing receiver's knowledge of how many SIM CLK
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218 cycles constitute an etu needs to change to the new value at exactly the
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219 correct moment in time, which is the moment immediately after the last byte
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220 (PCK) of the SIM's PPS response passes across the wire. If we were to rely on
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221 host software to decode all byte exchanges up to this point (ATR from the SIM,
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222 PPS request from ME/ID, then PPS response) and command the FPGA (UART in the
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223 other direction, or a modem control line) to switch the etu counters (the
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224 0.5 etu, 1 etu and 1.5 etu counters mentioned earlier in this document), we
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225 stand very little chance of getting this command to the FPGA in time, before
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226 ME/ID starts transmitting its next command to the SIM using the new etu
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227 definition.
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228
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229 Designs that incorporate a local CPU core immediately adjacent to the ISO 7816-3
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230 receiver block, such as original Osmocom SIMtrace in which the local CPU core
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231 and the ISO 7816-3 receiver sit in the same AT91SAMx chip, don't suffer from
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232 this problem: with a local (dedicated, embedded) CPU so close, the firmware can
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233 react and intervene in time. However, in the case of FC SIMsniff, the nearest
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234 CPU is the host computer separated by UART and USB links - not closely coupled
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235 enough to provide the degree of real-time response that is needed here. Someone
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236 could say that we should stick a soft CPU core with firmware into our FPGA - but
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237 we've implemented a different solution: we have a specialized PPS catcher state
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238 machine instead. This gateware FSM follows the spec-defined structure of ATR,
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239 PPS request and PPS response, and locates the two key items of interest to us:
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240
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241 * The PPS1 byte in the card's PPS response, which we check for a supported speed
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242 enhancement mode (the upper 6 bits need to match 0x94) and from which we
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243 extract the two lsbs selecting among D=8/16/32/64;
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244
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245 * The PCK byte that concludes the card's PPS response - the point where we throw
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246 the switch to sniffing with the new F/D ratio.