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annotate fpga/Makefile @ 52:cbfcc480d61b

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fpga build: migrate to yosys-tee wrapper
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 03 Oct 2023 18:17:58 +0000
parents 8be0b96b7c8d
children
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8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 SUBDIR= sniffer-basic sniffer-pps
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 all: ${SUBDIR}
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 ${SUBDIR}: FRC
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 cd $@; ${MAKE} ${MFLAGS}
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 clean: FRC
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
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9 rm -f a.out core errs
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 for i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11
8be0b96b7c8d fpga: add top Makefile across projects
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 FRC: